diff --git a/vendor/google_riscv-dv.lock.hjson b/vendor/google_riscv-dv.lock.hjson index 036e7aa8..4852610b 100644 --- a/vendor/google_riscv-dv.lock.hjson +++ b/vendor/google_riscv-dv.lock.hjson @@ -9,6 +9,6 @@ upstream: { url: https://github.com/google/riscv-dv - rev: e3e1e308cfc3d718aeb94bb3463371979d9a31ae + rev: d3419444ca2fdb499a204587b2d36c6f5c1e0c44 } } diff --git a/vendor/google_riscv-dv/README.md b/vendor/google_riscv-dv/README.md index 8ab6e23f..3e727628 100644 --- a/vendor/google_riscv-dv/README.md +++ b/vendor/google_riscv-dv/README.md @@ -7,12 +7,16 @@ processor verification. It currently supports the following features: - Supported privileged mode: machine mode, supervisor mode, user mode - Page table randomization and exception - Privileged CSR setup randomization +- Privileged CSR test suite - Trap/interrupt handling - Test suite to stress test MMU - Support sub-programs and random program calls - Support illegal instruction and HINT instruction - Random forward/backward branch instructions - Supports mixing directed instructions with random instruction stream +- Debug mode support, with fully randomized debug ROM +- Instruction generation coverage model +- Communication of information to any integrated SV testbench - Supports co-simulation with multiple ISS : spike, riscv-ovpsim A CSR test generation script written in Python is also provided, to generate a @@ -213,7 +217,7 @@ program. You can modify the link script to link each section to the target memory location. Please avoid setting a large memory range as it could takes a long time to randomly initializing the memory. You can break down a large memory region to a few representative small regions which covers all the boundary -conditions for the load/store testing. +conditions for the load/store testing. ### Runtime options of the generator @@ -224,8 +228,10 @@ conditions for the load/store testing. | num_of_sub_program | Number of sub-program in one test | 5 | | instr_cnt | Instruction count per test | 200 | | enable_page_table_exception | Enable page table exception | 0 | +| enable_unaligned_load_store | Enable unaligned memory operations | 0 | | no_ebreak | Disable ebreak instruction | 1 | | no_wfi | Disable WFI instruction | 1 | +| no_dret | Disable dret instruction | 1 | | no_branch_jump | Disable branch/jump instruction | 0 | | no_load_store | Disable load/store instruction | 0 | | no_csr_instr | Disable CSR instruction | 0 | @@ -239,6 +245,9 @@ conditions for the load/store testing. | enable_interrupt | Enable MStatus.MIE, used in interrupt test | 0 | | gen_debug_section | Disables randomized debug_rom section | 0 | | num_debug_sub_program | Number of debug sub-programs in test | 0 | +| enable_ebreak_in_debug_rom | Generate ebreak instructions inside debug ROM | 0 | +| set_dcsr_ebreak | Randomly enable dcsr.ebreak(m/s/u) | 0 | +| randomize_csr | Fully randomize main CSRs (xSTATUS, xIE) | 0 | ### Setup Privileged CSR description @@ -409,14 +418,6 @@ collaborative effort to build a strong open source RISC-V processor verification platform. Free feel to submit your pull request for review. Please refer to CONTRIBUTING.md for license related questions. -## Future release plan - -We have some work in progress which will be part of future releases: - -- Privileged CSR test suite. -- Coverage model. -- Debug mode support - ## Disclaimer This is not an officially supported Google product. diff --git a/vendor/google_riscv-dv/src/riscv_instr_gen_config.sv b/vendor/google_riscv-dv/src/riscv_instr_gen_config.sv index a6825176..74de5748 100644 --- a/vendor/google_riscv-dv/src/riscv_instr_gen_config.sv +++ b/vendor/google_riscv-dv/src/riscv_instr_gen_config.sv @@ -147,6 +147,7 @@ class riscv_instr_gen_config extends uvm_object; // - Accessing non-existence CSR // - Accessing CSR with wrong privileged mode bit enable_illegal_csr_instruction; + bit randomize_csr = 0; // sfence support bit allow_sfence_exception = 0; // Interrupt/Exception Delegation @@ -368,6 +369,7 @@ class riscv_instr_gen_config extends uvm_object; get_bool_arg_value("+force_m_delegation=", force_m_delegation); get_bool_arg_value("+force_s_delegation=", force_s_delegation); get_bool_arg_value("+require_signature_addr=", require_signature_addr); + get_bool_arg_value("+randomize_csr=", randomize_csr); if (this.require_signature_addr) begin get_hex_arg_value("+signature_addr=", signature_addr); end diff --git a/vendor/google_riscv-dv/src/riscv_privileged_common_seq.sv b/vendor/google_riscv-dv/src/riscv_privileged_common_seq.sv index ce362535..474b860c 100644 --- a/vendor/google_riscv-dv/src/riscv_privileged_common_seq.sv +++ b/vendor/google_riscv-dv/src/riscv_privileged_common_seq.sv @@ -55,8 +55,15 @@ class riscv_privileged_common_seq extends uvm_sequence; virtual function void setup_mmode_reg(privileged_mode_t mode, ref riscv_privil_reg regs[$]); mstatus = riscv_privil_reg::type_id::create("mstatus"); mstatus.init_reg(MSTATUS); - mstatus.set_val({cfg.mstatus[XLEN-1:XLEN-21], cfg.mstatus_tvm, cfg.mstatus_mxr, + if (cfg.randomize_csr) begin + mstatus.set_val({cfg.mstatus[XLEN-1:XLEN-21], cfg.mstatus_tvm, cfg.mstatus_mxr, cfg.mstatus_sum, cfg.mstatus_mprv, cfg.mstatus[16:0]}); + end else begin + mstatus.set_field("MPRV", cfg.mstatus_mprv); + mstatus.set_field("MXR", cfg.mstatus_mxr); + mstatus.set_field("SUM", cfg.mstatus_sum); + mstatus.set_field("TVM", cfg.mstatus_tvm); + end if(XLEN==64) begin mstatus.set_field("UXL", 2'b10); mstatus.set_field("SXL", 2'b10); @@ -67,10 +74,7 @@ class riscv_privileged_common_seq extends uvm_sequence; mstatus.set_field("UIE", 0); // Set the previous privileged mode as the target mode mstatus.set_field("MPP", mode); - if(mode == USER_MODE) - mstatus.set_field("SPP", 0); - else - mstatus.set_field("SPP", 1); + mstatus.set_field("SPP", 0); // Enable interrupt mstatus.set_field("MPIE", cfg.enable_interrupt); mstatus.set_field("MIE", cfg.enable_interrupt); @@ -84,7 +88,9 @@ class riscv_privileged_common_seq extends uvm_sequence; if (MIE inside {implemented_csr}) begin mie = riscv_privil_reg::type_id::create("mie"); mie.init_reg(MIE); - mie.set_val(cfg.mie); + if (cfg.randomize_csr) begin + mie.set_val(cfg.mie); + end mie.set_field("UEIE", cfg.enable_interrupt); mie.set_field("SEIE", cfg.enable_interrupt); mie.set_field("MEIE", cfg.enable_interrupt); @@ -105,7 +111,9 @@ class riscv_privileged_common_seq extends uvm_sequence; sstatus = riscv_privil_reg::type_id::create("sstatus"); sstatus.init_reg(SSTATUS); `DV_CHECK_RANDOMIZE_FATAL(sstatus, "cannot randomize sstatus") - sstatus.set_val(cfg.sstatus); + if (cfg.randomize_csr) begin + sstatus.set_val(cfg.sstatus); + end sstatus.set_field("SPIE", cfg.enable_interrupt); sstatus.set_field("SIE", cfg.enable_interrupt); sstatus.set_field("UPIE", cfg.enable_interrupt); @@ -117,16 +125,15 @@ class riscv_privileged_common_seq extends uvm_sequence; sstatus.set_field("FS", 0); sstatus.set_field("SD", 0); sstatus.set_field("UIE", 0); - if(mode == USER_MODE) - sstatus.set_field("SPP", 0); - else - sstatus.set_field("SPP", 1); + sstatus.set_field("SPP", 0); regs.push_back(sstatus); // Enable external and timer interrupt if (SIE inside {implemented_csr}) begin sie = riscv_privil_reg::type_id::create("sie"); sie.init_reg(SIE); - sie.set_val(cfg.sie); + if (cfg.randomize_csr) begin + sie.set_val(cfg.sie); + end sie.set_field("UEIE", cfg.enable_interrupt); sie.set_field("SEIE", cfg.enable_interrupt); sie.set_field("USIE", cfg.enable_interrupt); @@ -141,14 +148,18 @@ class riscv_privileged_common_seq extends uvm_sequence; ustatus = riscv_privil_reg::type_id::create("ustatus"); ustatus.init_reg(USTATUS); `DV_CHECK_RANDOMIZE_FATAL(ustatus, "cannot randomize ustatus") - ustatus.set_val(cfg.ustatus); + if (cfg.randomize_csr) begin + ustatus.set_val(cfg.ustatus); + end ustatus.set_field("UIE", cfg.enable_interrupt); ustatus.set_field("UPIE", cfg.enable_interrupt); regs.push_back(ustatus); if (UIE inside {implemented_csr}) begin uie = riscv_privil_reg::type_id::create("uie"); uie.init_reg(UIE); - uie.set_val(cfg.uie); + if (cfg.randomize_csr) begin + uie.set_val(cfg.uie); + end uie.set_field("UEIE", cfg.enable_interrupt); uie.set_field("USIE", cfg.enable_interrupt); uie.set_field("UTIE", 1'b0);