diff --git a/doc/cs_registers.rst b/doc/cs_registers.rst
index 85c77243..bed50d42 100644
--- a/doc/cs_registers.rst
+++ b/doc/cs_registers.rst
@@ -22,9 +22,11 @@ Ibex implements all the Control and Status Registers (CSRs) listed in the follow
 +---------+--------------------+--------+-----------------------------------------------+
 |  0x33F  | ``mhpmevent31``    | WARL   | Machine performance-monitoring event selector |
 +---------+--------------------+--------+-----------------------------------------------+
-|  0x341  | ``mepc``           | RW     | Machine Exception Program Counter             |
+|  0x340  | ``mscratch``       | RW     | Machine Scratch Register                      |
 +---------+--------------------+--------+-----------------------------------------------+
-|  0x342  | ``mcause``         | RW     | Machine Trap Cause                            |
+|  0x341  | ``mepc``           | WARL   | Machine Exception Program Counter             |
++---------+--------------------+--------+-----------------------------------------------+
+|  0x342  | ``mcause``         | WLRL   | Machine Cause Register                        |
 +---------+--------------------+--------+-----------------------------------------------+
 |  0x343  | ``mtval``          | WARL   | Machine Trap Value Register                   |
 +---------+--------------------+--------+-----------------------------------------------+
@@ -78,7 +80,7 @@ Reset Value: ``0x0000_1800``
 +-------+-----+---------------------------------------------------------------------------------+
 
 When an exception is encountered, MPIE will be set to MIE.
-When the ``mret`` instruction is executed, the value of MPIE will be stored back to IE.
+When the MRET instruction is executed, the value of MPIE will be stored back to IE.
 
 If you want to enable interrupt handling in your exception handler, set MIE to 1'b1 inside your handler code.
 
diff --git a/rtl/ibex_cs_registers.sv b/rtl/ibex_cs_registers.sv
index b266e82e..5d518822 100644
--- a/rtl/ibex_cs_registers.sv
+++ b/rtl/ibex_cs_registers.sv
@@ -152,6 +152,7 @@ module ibex_cs_registers #(
 
   // CSRs
   Status_t     mstatus_q, mstatus_n;
+  logic [31:0] mscratch_q, mscratch_n;
   logic [31:0] mepc_q, mepc_n;
   logic  [5:0] mcause_q, mcause_n;
   logic [31:0] mtval_q, mtval_n;
@@ -221,6 +222,8 @@ module ibex_cs_registers #(
       // misa
       CSR_MISA: csr_rdata_int = MISA_VALUE;
 
+      CSR_MSCRATCH: csr_rdata_int = mscratch_q;
+
       // mtvec: trap-vector base address
       CSR_MTVEC: csr_rdata_int = csr_mtvec_i;
 
@@ -284,6 +287,7 @@ module ibex_cs_registers #(
     exception_pc = pc_id_i;
 
     mstatus_n    = mstatus_q;
+    mscratch_n   = mscratch_q;
     mepc_n       = mepc_q;
     mcause_n     = mcause_q;
     mtval_n      = mtval_q;
@@ -307,6 +311,8 @@ module ibex_cs_registers #(
         end
       end
 
+      CSR_MSCRATCH: if (csr_we_int) mscratch_n = csr_wdata_int;
+
       // mepc: exception program counter
       CSR_MEPC: if (csr_we_int) mepc_n = {csr_wdata_int[31:1], 1'b0};
 
@@ -480,6 +486,7 @@ module ibex_cs_registers #(
           mpie: 1'b0,
           mpp:  PRIV_LVL_M
       };
+      mscratch_q <= '0;
       mepc_q     <= '0;
       mcause_q   <= '0;
       mtval_q    <= '0;
@@ -499,6 +506,7 @@ module ibex_cs_registers #(
           mpie: mstatus_n.mpie,
           mpp:  PRIV_LVL_M
       };
+      mscratch_q  <= mscratch_n;
       mepc_q      <= mepc_n;
       mcause_q    <= mcause_n;
       mtval_q     <= mtval_n;
diff --git a/rtl/ibex_defines.sv b/rtl/ibex_defines.sv
index 01804ac9..1b00d92f 100644
--- a/rtl/ibex_defines.sv
+++ b/rtl/ibex_defines.sv
@@ -205,6 +205,7 @@ typedef enum logic[11:0] {
   CSR_MTVEC     = 12'h305,
 
   // Machine trap handling
+  CSR_MSCRATCH  = 12'h340,
   CSR_MEPC      = 12'h341,
   CSR_MCAUSE    = 12'h342,
   CSR_MTVAL     = 12'h343,