diff --git a/prefetch_L0_buffer.sv b/prefetch_L0_buffer.sv
index 3e4d63ab..b0cdc376 100644
--- a/prefetch_L0_buffer.sv
+++ b/prefetch_L0_buffer.sv
@@ -122,7 +122,8 @@ module riscv_prefetch_L0_buffer
 
   always_comb
   begin
-    valid_unaligned = 1'b0;
+    valid_unaligned        = 1'b0;
+    rdata_unaligned[31:16] = 'x;
 
     if (valid_L0) begin
       case(addr_o[3:2])