diff --git a/controller.sv b/controller.sv index 48cfba6d..2c31799b 100644 --- a/controller.sv +++ b/controller.sv @@ -56,7 +56,6 @@ module controller // from prefetcher output logic instr_req_o, // Start fetching instructions - input logic instr_ack_i, // Acknow from instr memory or cache (means that data is available) // to prefetcher output logic pc_set_o, // jump to address set by pc_mux_sel @@ -222,7 +221,7 @@ module controller FIRST_FETCH: begin // Stall because of IF miss - if ((instr_ack_i == 1'b1) && (dbg_stall_i == 1'b0)) + if ((id_valid_i == 1'b1) && (dbg_stall_i == 1'b0)) begin ctrl_fsm_ns = DECODE; end diff --git a/cs_registers.sv b/cs_registers.sv index 271d2df3..a617f613 100644 --- a/cs_registers.sv +++ b/cs_registers.sv @@ -58,8 +58,7 @@ module cs_registers input logic is_compressed_i, // compressed instruction in ID input logic is_decoding_i, // controller is in DECODE state - input logic instr_fetch_i, // instruction fetch - + input logic imiss_i, // instruction fetch input logic jump_i, // jump instruction seen (j, jr, jal, jalr) input logic branch_i, // branch instruction seen (bf, bnf) input logic ld_stall_i, // load use hazard @@ -228,15 +227,15 @@ module cs_registers ///////////////////////////////////////////////////////////////// assign PCCR_in[0] = 1'b1; // cycle counter - assign PCCR_in[1] = id_valid_q & is_decoding_i; // instruction counter + assign PCCR_in[1] = id_valid_i & is_decoding_i; // instruction counter assign PCCR_in[2] = ld_stall_i & id_valid_q; // nr of load use hazards assign PCCR_in[3] = jr_stall_i & id_valid_q; // nr of jump register hazards - assign PCCR_in[4] = instr_fetch_i; // cycles waiting for instruction fetches + assign PCCR_in[4] = imiss_i; // cycles waiting for instruction fetches assign PCCR_in[5] = mem_load_i; // nr of loads assign PCCR_in[6] = mem_store_i; // nr of stores assign PCCR_in[7] = jump_i & id_valid_q; // nr of jumps (unconditional) assign PCCR_in[8] = branch_i & id_valid_q; // nr of branches (conditional) - assign PCCR_in[9] = id_valid_q & is_decoding_i & is_compressed_i; // compressed instruction counter + assign PCCR_in[9] = id_valid_i & is_decoding_i & is_compressed_i; // compressed instruction counter // assign external performance counters generate diff --git a/id_stage.sv b/id_stage.sv index 7d601318..7e22a9db 100644 --- a/id_stage.sv +++ b/id_stage.sv @@ -45,7 +45,6 @@ module id_stage // Interface to instruction memory input logic [31:0] instr_rdata_i, // comes from pipeline of IF stage output logic instr_req_o, - input logic instr_ack_i, // Jumps and branches output logic [1:0] jump_in_id_o, @@ -636,7 +635,6 @@ module id_stage // from prefetcher .instr_req_o ( instr_req_o ), - .instr_ack_i ( instr_ack_i ), // to prefetcher .pc_set_o ( pc_set_o ), diff --git a/if_stage.sv b/if_stage.sv index d69a8546..705edad4 100644 --- a/if_stage.sv +++ b/if_stage.sv @@ -46,7 +46,6 @@ module if_stage // instruction request control input logic req_i, - output logic valid_o, // instruction cache interface output logic instr_req_o, @@ -89,7 +88,8 @@ module if_stage output logic if_valid_o, // misc signals - output logic if_busy_o // is the IF stage busy fetching instructions? + output logic if_busy_o, // is the IF stage busy fetching instructions? + output logic perf_imiss_o // Instruction Fetch Miss ); // offset FSM @@ -100,6 +100,8 @@ module if_stage logic unaligned; logic unaligned_jump; + logic valid; + // prefetch buffer related signals logic prefetch_busy; logic branch_req, branch_req_Q; @@ -271,7 +273,7 @@ module if_stage fetch_ready = 1'b0; branch_req = 1'b0; - valid_o = 1'b0; + valid = 1'b0; unaligned = 1'b0; @@ -288,7 +290,7 @@ module if_stage // serving aligned 32 bit or 16 bit instruction, we don't know yet WAIT_ALIGNED: begin if (fetch_valid) begin - valid_o = 1'b1; // an instruction is ready for ID stage + valid = 1'b1; // an instruction is ready for ID stage if (req_i && if_valid_o) begin @@ -313,7 +315,7 @@ module if_stage if (fetch_valid) begin if (is_compressed[1]) begin - valid_o = 1'b1; // an instruction is ready for ID stage + valid = 1'b1; // an instruction is ready for ID stage if (req_i && if_valid_o) begin // next instruction will be aligned @@ -324,7 +326,7 @@ module if_stage // not compressed, we are looking at a 32 bit instruction if (fetch_unaligned_valid) begin - valid_o = 1'b1; // an instruction is ready for ID stage + valid = 1'b1; // an instruction is ready for ID stage if (req_i && if_valid_o) begin // next instruction will be unaligned @@ -347,7 +349,7 @@ module if_stage if (branch_req_Q == 1'b0) begin if (jump_in_ex_i == `BRANCH_COND) begin if (branch_decision_i) begin - valid_o = 1'b0; + valid = 1'b0; // branch taken branch_req = 1'b1; if (unaligned_jump) @@ -359,7 +361,7 @@ module if_stage end else if (jump_in_id_i == `BRANCH_JAL || jump_in_id_i == `BRANCH_JALR || pc_set_i || hwloop_jump_i) begin - valid_o = 1'b0; + valid = 1'b0; // switch to new PC from ID stage branch_req = 1'b1; @@ -374,6 +376,8 @@ module if_stage assign if_busy_o = prefetch_busy; + assign perf_imiss_o = (~fetch_valid) | branch_req; + // compressed instruction decoding, or more precisely compressed instruction // expander @@ -415,7 +419,7 @@ module if_stage end end - assign if_ready_o = valid_o & id_ready_i; + assign if_ready_o = valid & id_ready_i; assign if_valid_o = (~halt_if_i) & if_ready_o & (jump_in_id_i != `BRANCH_COND); endmodule diff --git a/prefetch_L0_buffer.sv b/prefetch_L0_buffer.sv index b5a3c184..f63dab45 100644 --- a/prefetch_L0_buffer.sv +++ b/prefetch_L0_buffer.sv @@ -65,11 +65,6 @@ module prefetch_L0_buffer logic valid_previous_chunk; logic clear_buffer; - logic [15:0] L0_buffer_misaligned; - - - assign L0_buffer_misaligned[15:0] = previous_chunk; - assign busy_o = (CS != EMPTY); diff --git a/riscv_core.sv b/riscv_core.sv index cddebf31..0f8d2821 100644 --- a/riscv_core.sv +++ b/riscv_core.sv @@ -178,7 +178,6 @@ module riscv_core // Signals between instruction core interface and pipe (if and id stages) logic instr_req_int; // Id stage asserts a req to instruction core interface - logic instr_ack_int; // instr core interface acks the request now (read data is available) // Interrupts logic irq_enable; @@ -211,6 +210,7 @@ module riscv_core logic dbg_set_npc; // Performance Counters + logic perf_imiss; logic perf_jump; logic perf_branch; logic perf_jr_stall; @@ -242,7 +242,6 @@ module riscv_core // instruction request control .req_i ( instr_req_int ), - .valid_o ( instr_ack_int ), // instruction cache interface .instr_req_o ( instr_req_o ), @@ -284,7 +283,8 @@ module riscv_core .id_ready_i ( id_ready ), .if_valid_o ( if_valid ), - .if_busy_o ( if_busy ) + .if_busy_o ( if_busy ), + .perf_imiss_o ( perf_imiss ) ); @@ -309,7 +309,6 @@ module riscv_core // Interface to instruction memory .instr_rdata_i ( instr_rdata_id ), .instr_req_o ( instr_req_int ), - .instr_ack_i ( instr_ack_int ), // Jumps and branches .jump_in_id_o ( jump_in_id ), @@ -573,8 +572,7 @@ module riscv_core .is_compressed_i ( is_compressed_id ), .is_decoding_i ( is_decoding ), - .instr_fetch_i ( ~instr_ack_int ), - + .imiss_i ( perf_imiss ), .jump_i ( perf_jump ), .branch_i ( perf_branch ), .ld_stall_i ( perf_ld_stall ),