diff --git a/if_stage.sv b/if_stage.sv
index 7f8008b0..2965eab8 100644
--- a/if_stage.sv
+++ b/if_stage.sv
@@ -84,6 +84,7 @@ module riscv_if_stage
 
     // from debug unit
     input  logic [31:0] dbg_npc_i,
+    input  logic        dbg_set_npc_i,
 
     // pipeline stall
     input  logic        halt_if_i,
@@ -350,7 +351,7 @@ module riscv_if_stage
 
     // take care of jumps and branches
     // only send one branch request per jump/branch
-    if (branch_req_Q == 1'b0) begin
+    if (dbg_set_npc_i || (branch_req_Q == 1'b0)) begin
       if (pc_set_i) begin
         valid   = 1'b0;
 
diff --git a/riscv_core.sv b/riscv_core.sv
index cdd1ff28..ff487d82 100644
--- a/riscv_core.sv
+++ b/riscv_core.sv
@@ -274,6 +274,7 @@ module riscv_core
 
     // from debug unit
     .dbg_npc_i           ( dbg_npc         ),
+    .dbg_set_npc_i       ( dbg_set_npc     ),
 
     // Jump and branch target and decision
     .jump_in_id_i        ( jump_in_id      ),