diff --git a/examples/simple_system/README.md b/examples/simple_system/README.md
index 9a921b9a..7fb1c271 100644
--- a/examples/simple_system/README.md
+++ b/examples/simple_system/README.md
@@ -99,7 +99,7 @@ The simulator produces several output files
 Similar to the Verilator flow the Simple System simulator binary can be built using:
 
 ```
-fusesoc --cores-root=. run --target=sim --tool=vcs --setup --build lowrisc:ibex:ibex_simple_system --RV32M=1 --RV32E=0 --SRAM_INIT_FILE=`<sw_vmem_file>`
+fusesoc --cores-root=. run --target=sim --tool=vcs --setup --build lowrisc:ibex:ibex_simple_system --RV32M=1 --RV32E=0 --SRAMInitFile=`<sw_vmem_file>`
 ```
 
 `<sw_vmem_file>` should be a path to a vmem file built as described above, use
@@ -119,7 +119,7 @@ Pass `-gui` to use the DVE GUI.
 To build and run Simple System run:
 
 ```
-fusesoc --cores-root=. run --target=sim --tool=rivierapro lowrisc:ibex:ibex_simple_system --RV32M=1 --RV32E=0 --SRAM_INIT_FILE=<sw_vmem_file>
+fusesoc --cores-root=. run --target=sim --tool=rivierapro lowrisc:ibex:ibex_simple_system --RV32M=1 --RV32E=0 --SRAMInitFile=<sw_vmem_file>
 ```
 
 `<sw_vmem_file>` should be a path to a vmem file built as described above, use
diff --git a/examples/simple_system/ibex_simple_system.core b/examples/simple_system/ibex_simple_system.core
index f5aa9fe2..854962fe 100644
--- a/examples/simple_system/ibex_simple_system.core
+++ b/examples/simple_system/ibex_simple_system.core
@@ -5,20 +5,21 @@ CAPI=2:
 name: "lowrisc:ibex:ibex_simple_system"
 description: "Generic simple system for running binaries on ibex using verilator"
 filesets:
-  files_sim_verilator:
+  files_sim:
+    depend:
+      - lowrisc:ibex:ibex_core_tracing
+      - lowrisc:ibex:sim_shared
+    files:
+      - rtl/ibex_simple_system.sv
+    file_type: systemVerilogSource
+
+  files_verilator:
     depend:
       - lowrisc:dv_verilator:memutil_verilator
       - lowrisc:dv_verilator:simutil_verilator
-      - lowrisc:ibex:ibex_core_tracing
-      - lowrisc:ibex:sim_shared
       - lowrisc:dv_verilator:ibex_pcounts
     files:
-      - rtl/ibex_simple_system.sv
       - ibex_simple_system.cc: { file_type: cppSource }
-    file_type: systemVerilogSource
-
-  files_verilator_waiver:
-    files:
       - lint/verilator_waiver.vlt: {file_type: vlt}
 
 
@@ -41,9 +42,9 @@ parameters:
     paramtype: vlogdefine
     description: "Bitmanip implementation parameter enum. See ibex_pkg.sv (EXPERIMENTAL)"
 
-  SRAM_INIT_FILE:
+  SRAMInitFile:
     datatype: str
-    paramtype: vlogdefine
+    paramtype: vlogparam
     description: "Path to a vmem file to initialize the RAM with"
 
   MultiplierImplementation:
@@ -85,8 +86,8 @@ parameters:
 targets:
   default: &default_target
     filesets:
-      - tool_verilator ? (files_verilator_waiver)
-      - files_sim_verilator
+      - tool_verilator ? (files_verilator)
+      - files_sim
     toplevel: ibex_simple_system
 
   sim:
@@ -102,7 +103,7 @@ targets:
       - PMPEnable
       - PMPGranularity
       - PMPNumRegions
-      - SRAM_INIT_FILE
+      - SRAMInitFile
     tools:
       vcs:
         vcs_options:
diff --git a/examples/simple_system/rtl/ibex_simple_system.sv b/examples/simple_system/rtl/ibex_simple_system.sv
index 23926e1a..7e8f7c16 100644
--- a/examples/simple_system/rtl/ibex_simple_system.sv
+++ b/examples/simple_system/rtl/ibex_simple_system.sv
@@ -32,6 +32,7 @@ module ibex_simple_system (
   parameter bit               BranchTargetALU          = 1'b0;
   parameter bit               WritebackStage           = 1'b0;
   parameter                   MultiplierImplementation = "fast";
+  parameter                   SRAMInitFile             = "";
 
   logic clk_sys = 1'b0, rst_sys_n;
 
@@ -198,7 +199,8 @@ module ibex_simple_system (
 
   // SRAM block for instruction and data storage
   ram_2p #(
-      .Depth(1024*1024/4)
+      .Depth(1024*1024/4),
+      .MemInitFile(SRAMInitFile)
     ) u_ram (
       .clk_i       (clk_sys),
       .rst_ni      (rst_sys_n),