diff --git a/cs_registers.sv b/cs_registers.sv
index 08619cd6..da14efa7 100644
--- a/cs_registers.sv
+++ b/cs_registers.sv
@@ -99,6 +99,7 @@ module cs_registers
   // address decoder for constant CSRs
   always_comb
   begin
+    constant_rdata_int = '0;
     is_constant = 1'b1;
     unique case (csr_addr_i)
       12'hF00: constant_rdata_int = 32'h00_00_01_00;  // mcpuid: RV32I
@@ -112,6 +113,7 @@ module cs_registers
   // address decoder for regular CSRs
   always_comb
   begin
+    csr_index = '0;
     is_register = 1'b1;
     unique case (csr_addr_i)
       12'h340: csr_index = `CSR_IDX_MSCRATCH;
diff --git a/wb_stage.sv b/wb_stage.sv
index 37a84a2c..b10c5063 100644
--- a/wb_stage.sv
+++ b/wb_stage.sv
@@ -55,9 +55,10 @@ module wb_stage
    // 1:    From Data Memory
    always_comb
    begin : REGFILE_WDATA_MUX
-      casex (regfile_wdata_mux_sel_i)
-        //1'b0:  begin regfile_wdata_o <= sp_rdata_i;        end
-        1'b1:  begin regfile_wdata_o <= data_rdata_i;      end
+      case (regfile_wdata_mux_sel_i)
+        //1'b0:  regfile_wdata_o <= sp_rdata_i;
+        1'b1:    regfile_wdata_o <= data_rdata_i;
+        default: regfile_wdata_o <= data_rdata_i;
       endcase; // case (regfile_wdata_mux_sel_i)
    end