diff --git a/examples/fpga/artya7/README.md b/examples/fpga/artya7/README.md
deleted file mode 100644
index f897c89b..00000000
--- a/examples/fpga/artya7/README.md
+++ /dev/null
@@ -1,95 +0,0 @@
-# Ibex RISC-V Core SoC Example
-
-Please see [examples](https://ibex-core.readthedocs.io/en/latest/02_user/examples.html "Ibex User Manual") for a description of this example.
-
-## Requirements
-
-### Tools
-
-  - RV32 compiler
-  - srecord
-  - `fusesoc` and its dependencies
-  - Xilinx Vivado
-
-### Hardware
-
-  - Either a Digilent Arty A7-35 oder A7-100 board
-
-## Build
-
-The easiest way to build and execute this example is to call the following make goals from the root directory.
-
-Use the following for the Arty A7-35
-
-```
-make build-arty-35 program-arty
-```
-
-and for the Arty A7-100
-
-```
-make build-arty-100 program-arty
-```
-
-### Software
-
-First the software must be built. Go into `examples/sw/led` and call:
-
-```
-make CC=/path/to/RISC-V-compiler
-```
-
-The setting of `CC` is only required if `riscv32-unknown-elf-gcc` is not available through the `PATH` environment variable.
-The path to the RV32 compiler `/path/to/RISC-V-compiler` depends on the environment.
-For example, it can be for example `/opt/riscv/bin/riscv-none-embed-gcc` if the whole path is required or simply the name of the executable if it is available through the `PATH` environment variable.
-
-This should produce a `led.vmem` file which is used in the synthesis to update the SRAM storage.
-
-
-
-### Hardware
-
-Run either of the following commands at the top level to build the respective hardware.
-Both variants of the Arty A7 are supported and can be selected via the `--parts` parameter.
-
-```
-fusesoc --cores-root=. run --target=synth --setup --build lowrisc:ibex:top_artya7 --part xc7a35ticsg324-1L
-```
-
-```
-fusesoc --cores-root=. run --target=synth --setup --build lowrisc:ibex:top_artya7 --part xc7a100tcsg324-1
-```
-
-This will create a directory `build` which contains the output files, including
-the bitstream.
-
-
-Initial memory parameter `SRAMInitFile` can be given to FuseSoc to specify which .vmem file to load the design with.
-Example use case includes loading `coremark.vmem` which can be used for performance/power analysis.
-
-Please see [CoreMark README](https://github.com/lowRISC/ibex/blob/master/examples/sw/benchmarks/README.md) for compiling CoreMark.
-
-```
-fusesoc --cores-root=. run --target=synth --setup --build lowrisc:ibex:top_artya7 --part xc7a100tcsg324-1 --SRAMInitFile=examples/sw/benchmarks/coremark/coremark.vmem
-```
-
-#### Power Analysis Using Vivado
-
-Setting `FPGAPowerAnalysis` parameter to 1 allows user to run a power analysis using Vivado.
-It uses a post-implementation functional simulation on Vivado to log switching activity.
-This switching activity is then used to generate a detailed power report.
-In order to use it with CoreMark run the command below
-
-```
-fusesoc --cores-root=. run --target=synth --setup --build lowrisc:ibex:top_artya7 --part xc7a100tcsg324-1 --SRAMInitFile=examples/sw/benchmarks/coremark/coremark.vmem --FPGAPowerAnalysis=1
-```
-
-## Program
-
-After the board is connected to the computer it can be programmed with:
-
-```
-fusesoc --cores-root=. run --target=synth --run lowrisc:ibex:top_artya7
-```
-
-LED1/LED3 and LED0/LED2 should alternately be on after the FPGA programming is finished.
diff --git a/examples/fpga/artya7/data/pins_artya7.xdc b/examples/fpga/artya7/data/pins_artya7.xdc
deleted file mode 100644
index a43b31bc..00000000
--- a/examples/fpga/artya7/data/pins_artya7.xdc
+++ /dev/null
@@ -1,217 +0,0 @@
-## Based on https://github.com/Digilent/digilent-xdc/blob/master/Arty-A7-100-Master.xdc
-## This file is a general .xdc for the Arty A7-100 Rev. D
-## To use it in a project:
-## - uncomment the lines corresponding to used pins
-## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
-
-## Clock signal
-set_property -dict { PACKAGE_PIN E3    IOSTANDARD LVCMOS33 } [get_ports { IO_CLK }]; #IO_L12P_T1_MRCC_35 Sch=gclk[100]
-create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports { IO_CLK }];
-
-## Switches
-#set_property -dict { PACKAGE_PIN A8    IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L12N_T1_MRCC_16 Sch=sw[0]
-#set_property -dict { PACKAGE_PIN C11   IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L13P_T2_MRCC_16 Sch=sw[1]
-#set_property -dict { PACKAGE_PIN C10   IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L13N_T2_MRCC_16 Sch=sw[2]
-#set_property -dict { PACKAGE_PIN A10   IOSTANDARD LVCMOS33 } [get_ports { sw[3] }]; #IO_L14P_T2_SRCC_16 Sch=sw[3]
-
-## RGB LEDs
-#set_property -dict { PACKAGE_PIN E1    IOSTANDARD LVCMOS33 } [get_ports { led0_b }]; #IO_L18N_T2_35 Sch=led0_b
-#set_property -dict { PACKAGE_PIN F6    IOSTANDARD LVCMOS33 } [get_ports { led0_g }]; #IO_L19N_T3_VREF_35 Sch=led0_g
-#set_property -dict { PACKAGE_PIN G6    IOSTANDARD LVCMOS33 } [get_ports { led0_r }]; #IO_L19P_T3_35 Sch=led0_r
-#set_property -dict { PACKAGE_PIN G4    IOSTANDARD LVCMOS33 } [get_ports { led1_b }]; #IO_L20P_T3_35 Sch=led1_b
-#set_property -dict { PACKAGE_PIN J4    IOSTANDARD LVCMOS33 } [get_ports { led1_g }]; #IO_L21P_T3_DQS_35 Sch=led1_g
-#set_property -dict { PACKAGE_PIN G3    IOSTANDARD LVCMOS33 } [get_ports { led1_r }]; #IO_L20N_T3_35 Sch=led1_r
-#set_property -dict { PACKAGE_PIN H4    IOSTANDARD LVCMOS33 } [get_ports { led2_b }]; #IO_L21N_T3_DQS_35 Sch=led2_b
-#set_property -dict { PACKAGE_PIN J2    IOSTANDARD LVCMOS33 } [get_ports { led2_g }]; #IO_L22N_T3_35 Sch=led2_g
-#set_property -dict { PACKAGE_PIN J3    IOSTANDARD LVCMOS33 } [get_ports { led2_r }]; #IO_L22P_T3_35 Sch=led2_r
-#set_property -dict { PACKAGE_PIN K2    IOSTANDARD LVCMOS33 } [get_ports { led3_b }]; #IO_L23P_T3_35 Sch=led3_b
-#set_property -dict { PACKAGE_PIN H6    IOSTANDARD LVCMOS33 } [get_ports { led3_g }]; #IO_L24P_T3_35 Sch=led3_g
-#set_property -dict { PACKAGE_PIN K1    IOSTANDARD LVCMOS33 } [get_ports { led3_r }]; #IO_L23N_T3_35 Sch=led3_r
-
-## LEDs
-set_property -dict { PACKAGE_PIN H5    IOSTANDARD LVCMOS33 } [get_ports { LED[0] }]; #IO_L24N_T3_35 Sch=led[4]
-set_property -dict { PACKAGE_PIN J5    IOSTANDARD LVCMOS33 } [get_ports { LED[1] }]; #IO_25_35 Sch=led[5]
-set_property -dict { PACKAGE_PIN T9    IOSTANDARD LVCMOS33 } [get_ports { LED[2] }]; #IO_L24P_T3_A01_D17_14 Sch=led[6]
-set_property -dict { PACKAGE_PIN T10   IOSTANDARD LVCMOS33 } [get_ports { LED[3] }]; #IO_L24N_T3_A00_D16_14 Sch=led[7]
-
-## Buttons
-#set_property -dict { PACKAGE_PIN D9    IOSTANDARD LVCMOS33 } [get_ports { btn[0] }]; #IO_L6N_T0_VREF_16 Sch=btn[0]
-#set_property -dict { PACKAGE_PIN C9    IOSTANDARD LVCMOS33 } [get_ports { btn[1] }]; #IO_L11P_T1_SRCC_16 Sch=btn[1]
-#set_property -dict { PACKAGE_PIN B9    IOSTANDARD LVCMOS33 } [get_ports { btn[2] }]; #IO_L11N_T1_SRCC_16 Sch=btn[2]
-#set_property -dict { PACKAGE_PIN B8    IOSTANDARD LVCMOS33 } [get_ports { btn[3] }]; #IO_L12P_T1_MRCC_16 Sch=btn[3]
-
-## Pmod Header JA
-#set_property -dict { PACKAGE_PIN G13   IOSTANDARD LVCMOS33 } [get_ports { ja[0] }]; #IO_0_15 Sch=ja[1]
-#set_property -dict { PACKAGE_PIN B11   IOSTANDARD LVCMOS33 } [get_ports { ja[1] }]; #IO_L4P_T0_15 Sch=ja[2]
-#set_property -dict { PACKAGE_PIN A11   IOSTANDARD LVCMOS33 } [get_ports { ja[2] }]; #IO_L4N_T0_15 Sch=ja[3]
-#set_property -dict { PACKAGE_PIN D12   IOSTANDARD LVCMOS33 } [get_ports { ja[3] }]; #IO_L6P_T0_15 Sch=ja[4]
-#set_property -dict { PACKAGE_PIN D13   IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L6N_T0_VREF_15 Sch=ja[7]
-#set_property -dict { PACKAGE_PIN B18   IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L10P_T1_AD11P_15 Sch=ja[8]
-#set_property -dict { PACKAGE_PIN A18   IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L10N_T1_AD11N_15 Sch=ja[9]
-#set_property -dict { PACKAGE_PIN K16   IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_25_15 Sch=ja[10]
-
-## Pmod Header JB
-#set_property -dict { PACKAGE_PIN E15   IOSTANDARD LVCMOS33 } [get_ports { jb[0] }]; #IO_L11P_T1_SRCC_15 Sch=jb_p[1]
-#set_property -dict { PACKAGE_PIN E16   IOSTANDARD LVCMOS33 } [get_ports { jb[1] }]; #IO_L11N_T1_SRCC_15 Sch=jb_n[1]
-#set_property -dict { PACKAGE_PIN D15   IOSTANDARD LVCMOS33 } [get_ports { jb[2] }]; #IO_L12P_T1_MRCC_15 Sch=jb_p[2]
-#set_property -dict { PACKAGE_PIN C15   IOSTANDARD LVCMOS33 } [get_ports { jb[3] }]; #IO_L12N_T1_MRCC_15 Sch=jb_n[2]
-#set_property -dict { PACKAGE_PIN J17   IOSTANDARD LVCMOS33 } [get_ports { jb[4] }]; #IO_L23P_T3_FOE_B_15 Sch=jb_p[3]
-#set_property -dict { PACKAGE_PIN J18   IOSTANDARD LVCMOS33 } [get_ports { jb[5] }]; #IO_L23N_T3_FWE_B_15 Sch=jb_n[3]
-#set_property -dict { PACKAGE_PIN K15   IOSTANDARD LVCMOS33 } [get_ports { jb[6] }]; #IO_L24P_T3_RS1_15 Sch=jb_p[4]
-#set_property -dict { PACKAGE_PIN J15   IOSTANDARD LVCMOS33 } [get_ports { jb[7] }]; #IO_L24N_T3_RS0_15 Sch=jb_n[4]
-
-## Pmod Header JC
-#set_property -dict { PACKAGE_PIN U12   IOSTANDARD LVCMOS33 } [get_ports { jc[0] }]; #IO_L20P_T3_A08_D24_14 Sch=jc_p[1]
-#set_property -dict { PACKAGE_PIN V12   IOSTANDARD LVCMOS33 } [get_ports { jc[1] }]; #IO_L20N_T3_A07_D23_14 Sch=jc_n[1]
-#set_property -dict { PACKAGE_PIN V10   IOSTANDARD LVCMOS33 } [get_ports { jc[2] }]; #IO_L21P_T3_DQS_14 Sch=jc_p[2]
-#set_property -dict { PACKAGE_PIN V11   IOSTANDARD LVCMOS33 } [get_ports { jc[3] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=jc_n[2]
-#set_property -dict { PACKAGE_PIN U14   IOSTANDARD LVCMOS33 } [get_ports { jc[4] }]; #IO_L22P_T3_A05_D21_14 Sch=jc_p[3]
-#set_property -dict { PACKAGE_PIN V14   IOSTANDARD LVCMOS33 } [get_ports { jc[5] }]; #IO_L22N_T3_A04_D20_14 Sch=jc_n[3]
-#set_property -dict { PACKAGE_PIN T13   IOSTANDARD LVCMOS33 } [get_ports { jc[6] }]; #IO_L23P_T3_A03_D19_14 Sch=jc_p[4]
-#set_property -dict { PACKAGE_PIN U13   IOSTANDARD LVCMOS33 } [get_ports { jc[7] }]; #IO_L23N_T3_A02_D18_14 Sch=jc_n[4]
-
-## Pmod Header JD
-#set_property -dict { PACKAGE_PIN D4    IOSTANDARD LVCMOS33 } [get_ports { jd[0] }]; #IO_L11N_T1_SRCC_35 Sch=jd[1]
-#set_property -dict { PACKAGE_PIN D3    IOSTANDARD LVCMOS33 } [get_ports { jd[1] }]; #IO_L12N_T1_MRCC_35 Sch=jd[2]
-#set_property -dict { PACKAGE_PIN F4    IOSTANDARD LVCMOS33 } [get_ports { jd[2] }]; #IO_L13P_T2_MRCC_35 Sch=jd[3]
-#set_property -dict { PACKAGE_PIN F3    IOSTANDARD LVCMOS33 } [get_ports { jd[3] }]; #IO_L13N_T2_MRCC_35 Sch=jd[4]
-#set_property -dict { PACKAGE_PIN E2    IOSTANDARD LVCMOS33 } [get_ports { jd[4] }]; #IO_L14P_T2_SRCC_35 Sch=jd[7]
-#set_property -dict { PACKAGE_PIN D2    IOSTANDARD LVCMOS33 } [get_ports { jd[5] }]; #IO_L14N_T2_SRCC_35 Sch=jd[8]
-#set_property -dict { PACKAGE_PIN H2    IOSTANDARD LVCMOS33 } [get_ports { jd[6] }]; #IO_L15P_T2_DQS_35 Sch=jd[9]
-#set_property -dict { PACKAGE_PIN G2    IOSTANDARD LVCMOS33 } [get_ports { jd[7] }]; #IO_L15N_T2_DQS_35 Sch=jd[10]
-
-## USB-UART Interface
-#set_property -dict { PACKAGE_PIN D10   IOSTANDARD LVCMOS33 } [get_ports { uart_rxd_out }]; #IO_L19N_T3_VREF_16 Sch=uart_rxd_out
-#set_property -dict { PACKAGE_PIN A9    IOSTANDARD LVCMOS33 } [get_ports { uart_txd_in }]; #IO_L14N_T2_SRCC_16 Sch=uart_txd_in
-
-## ChipKit Outer Digital Header
-#set_property -dict { PACKAGE_PIN V15   IOSTANDARD LVCMOS33 } [get_ports { ck_io0  }]; #IO_L16P_T2_CSI_B_14 Sch=ck_io[0]
-#set_property -dict { PACKAGE_PIN U16   IOSTANDARD LVCMOS33 } [get_ports { ck_io1  }]; #IO_L18P_T2_A12_D28_14 Sch=ck_io[1]
-#set_property -dict { PACKAGE_PIN P14   IOSTANDARD LVCMOS33 } [get_ports { ck_io2  }]; #IO_L8N_T1_D12_14 Sch=ck_io[2]
-#set_property -dict { PACKAGE_PIN T11   IOSTANDARD LVCMOS33 } [get_ports { ck_io3  }]; #IO_L19P_T3_A10_D26_14 Sch=ck_io[3]
-#set_property -dict { PACKAGE_PIN R12   IOSTANDARD LVCMOS33 } [get_ports { ck_io4  }]; #IO_L5P_T0_D06_14 Sch=ck_io[4]
-#set_property -dict { PACKAGE_PIN T14   IOSTANDARD LVCMOS33 } [get_ports { ck_io5  }]; #IO_L14P_T2_SRCC_14 Sch=ck_io[5]
-#set_property -dict { PACKAGE_PIN T15   IOSTANDARD LVCMOS33 } [get_ports { ck_io6  }]; #IO_L14N_T2_SRCC_14 Sch=ck_io[6]
-#set_property -dict { PACKAGE_PIN T16   IOSTANDARD LVCMOS33 } [get_ports { ck_io7  }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=ck_io[7]
-#set_property -dict { PACKAGE_PIN N15   IOSTANDARD LVCMOS33 } [get_ports { ck_io8  }]; #IO_L11P_T1_SRCC_14 Sch=ck_io[8]
-#set_property -dict { PACKAGE_PIN M16   IOSTANDARD LVCMOS33 } [get_ports { ck_io9  }]; #IO_L10P_T1_D14_14 Sch=ck_io[9]
-#set_property -dict { PACKAGE_PIN V17   IOSTANDARD LVCMOS33 } [get_ports { ck_io10 }]; #IO_L18N_T2_A11_D27_14 Sch=ck_io[10]
-#set_property -dict { PACKAGE_PIN U18   IOSTANDARD LVCMOS33 } [get_ports { ck_io11 }]; #IO_L17N_T2_A13_D29_14 Sch=ck_io[11]
-#set_property -dict { PACKAGE_PIN R17   IOSTANDARD LVCMOS33 } [get_ports { ck_io12 }]; #IO_L12N_T1_MRCC_14 Sch=ck_io[12]
-#set_property -dict { PACKAGE_PIN P17   IOSTANDARD LVCMOS33 } [get_ports { ck_io13 }]; #IO_L12P_T1_MRCC_14 Sch=ck_io[13]
-
-## ChipKit Inner Digital Header
-#set_property -dict { PACKAGE_PIN U11   IOSTANDARD LVCMOS33 } [get_ports { ck_io26 }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=ck_io[26]
-#set_property -dict { PACKAGE_PIN V16   IOSTANDARD LVCMOS33 } [get_ports { ck_io27 }]; #IO_L16N_T2_A15_D31_14 Sch=ck_io[27]
-#set_property -dict { PACKAGE_PIN M13   IOSTANDARD LVCMOS33 } [get_ports { ck_io28 }]; #IO_L6N_T0_D08_VREF_14 Sch=ck_io[28]
-#set_property -dict { PACKAGE_PIN R10   IOSTANDARD LVCMOS33 } [get_ports { ck_io29 }]; #IO_25_14 Sch=ck_io[29]
-#set_property -dict { PACKAGE_PIN R11   IOSTANDARD LVCMOS33 } [get_ports { ck_io30 }]; #IO_0_14 Sch=ck_io[30]
-#set_property -dict { PACKAGE_PIN R13   IOSTANDARD LVCMOS33 } [get_ports { ck_io31 }]; #IO_L5N_T0_D07_14 Sch=ck_io[31]
-#set_property -dict { PACKAGE_PIN R15   IOSTANDARD LVCMOS33 } [get_ports { ck_io32 }]; #IO_L13N_T2_MRCC_14 Sch=ck_io[32]
-#set_property -dict { PACKAGE_PIN P15   IOSTANDARD LVCMOS33 } [get_ports { ck_io33 }]; #IO_L13P_T2_MRCC_14 Sch=ck_io[33]
-#set_property -dict { PACKAGE_PIN R16   IOSTANDARD LVCMOS33 } [get_ports { ck_io34 }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=ck_io[34]
-#set_property -dict { PACKAGE_PIN N16   IOSTANDARD LVCMOS33 } [get_ports { ck_io35 }]; #IO_L11N_T1_SRCC_14 Sch=ck_io[35]
-#set_property -dict { PACKAGE_PIN N14   IOSTANDARD LVCMOS33 } [get_ports { ck_io36 }]; #IO_L8P_T1_D11_14 Sch=ck_io[36]
-#set_property -dict { PACKAGE_PIN U17   IOSTANDARD LVCMOS33 } [get_ports { ck_io37 }]; #IO_L17P_T2_A14_D30_14 Sch=ck_io[37]
-#set_property -dict { PACKAGE_PIN T18   IOSTANDARD LVCMOS33 } [get_ports { ck_io38 }]; #IO_L7N_T1_D10_14 Sch=ck_io[38]
-#set_property -dict { PACKAGE_PIN R18   IOSTANDARD LVCMOS33 } [get_ports { ck_io39 }]; #IO_L7P_T1_D09_14 Sch=ck_io[39]
-#set_property -dict { PACKAGE_PIN P18   IOSTANDARD LVCMOS33 } [get_ports { ck_io40 }]; #IO_L9N_T1_DQS_D13_14 Sch=ck_io[40]
-#set_property -dict { PACKAGE_PIN N17   IOSTANDARD LVCMOS33 } [get_ports { ck_io41 }]; #IO_L9P_T1_DQS_14 Sch=ck_io[41]
-
-## ChipKit Outer Analog Header - as Single-Ended Analog Inputs
-## NOTE: These ports can be used as single-ended analog inputs with voltages from 0-3.3V (ChipKit analog pins A0-A5) or as digital I/O.
-## WARNING: Do not use both sets of constraints at the same time!
-## NOTE: The following constraints should be used with the XADC IP core when using these ports as analog inputs.
-#set_property -dict { PACKAGE_PIN C5    IOSTANDARD LVCMOS33 } [get_ports { vaux4_n  }]; #IO_L1N_T0_AD4N_35 	   Sch=ck_an_n[0] ChipKit pin=A0
-#set_property -dict { PACKAGE_PIN C6    IOSTANDARD LVCMOS33 } [get_ports { vaux4_p  }]; #IO_L1P_T0_AD4P_35 	   Sch=ck_an_p[0] ChipKit pin=A0
-#set_property -dict { PACKAGE_PIN A5    IOSTANDARD LVCMOS33 } [get_ports { vaux5_n  }]; #IO_L3N_T0_DQS_AD5N_35 Sch=ck_an_n[1] ChipKit pin=A1
-#set_property -dict { PACKAGE_PIN A6    IOSTANDARD LVCMOS33 } [get_ports { vaux5_p  }]; #IO_L3P_T0_DQS_AD5P_35 Sch=ck_an_p[1] ChipKit pin=A1
-#set_property -dict { PACKAGE_PIN B4    IOSTANDARD LVCMOS33 } [get_ports { vaux6_n  }]; #IO_L7N_T1_AD6N_35 	   Sch=ck_an_n[2] ChipKit pin=A2
-#set_property -dict { PACKAGE_PIN C4    IOSTANDARD LVCMOS33 } [get_ports { vaux6_p  }]; #IO_L7P_T1_AD6P_35 	   Sch=ck_an_p[2] ChipKit pin=A2
-#set_property -dict { PACKAGE_PIN A1    IOSTANDARD LVCMOS33 } [get_ports { vaux7_n  }]; #IO_L9N_T1_DQS_AD7N_35 Sch=ck_an_n[3] ChipKit pin=A3
-#set_property -dict { PACKAGE_PIN B1    IOSTANDARD LVCMOS33 } [get_ports { vaux7_p  }]; #IO_L9P_T1_DQS_AD7P_35 Sch=ck_an_p[3] ChipKit pin=A3
-#set_property -dict { PACKAGE_PIN B2    IOSTANDARD LVCMOS33 } [get_ports { vaux15_n }]; #IO_L10N_T1_AD15N_35   Sch=ck_an_n[4] ChipKit pin=A4
-#set_property -dict { PACKAGE_PIN B3    IOSTANDARD LVCMOS33 } [get_ports { vaux15_p }]; #IO_L10P_T1_AD15P_35   Sch=ck_an_p[4] ChipKit pin=A4
-#set_property -dict { PACKAGE_PIN C14   IOSTANDARD LVCMOS33 } [get_ports { vaux0_n  }]; #IO_L1N_T0_AD0N_15 	   Sch=ck_an_n[5] ChipKit pin=A5
-#set_property -dict { PACKAGE_PIN D14   IOSTANDARD LVCMOS33 } [get_ports { vaux0_p  }]; #IO_L1P_T0_AD0P_15 	   Sch=ck_an_p[5] ChipKit pin=A5
-## ChipKit Outer Analog Header - as Digital I/O
-## NOTE: The following constraints should be used when using these ports as digital I/O.
-#set_property -dict { PACKAGE_PIN F5    IOSTANDARD LVCMOS33 } [get_ports { ck_a0 }]; #IO_0_35 Sch=ck_a[0]
-#set_property -dict { PACKAGE_PIN D8    IOSTANDARD LVCMOS33 } [get_ports { ck_a1 }]; #IO_L4P_T0_35 Sch=ck_a[1]
-#set_property -dict { PACKAGE_PIN C7    IOSTANDARD LVCMOS33 } [get_ports { ck_a2 }]; #IO_L4N_T0_35 Sch=ck_a[2]
-#set_property -dict { PACKAGE_PIN E7    IOSTANDARD LVCMOS33 } [get_ports { ck_a3 }]; #IO_L6P_T0_35 Sch=ck_a[3]
-#set_property -dict { PACKAGE_PIN D7    IOSTANDARD LVCMOS33 } [get_ports { ck_a4 }]; #IO_L6N_T0_VREF_35 Sch=ck_a[4]
-#set_property -dict { PACKAGE_PIN D5    IOSTANDARD LVCMOS33 } [get_ports { ck_a5 }]; #IO_L11P_T1_SRCC_35 Sch=ck_a[5]
-
-## ChipKit Inner Analog Header - as Differential Analog Inputs
-## NOTE: These ports can be used as differential analog inputs with voltages from 0-1.0V (ChipKit analog pins A6-A11) or as digital I/O.
-## WARNING: Do not use both sets of constraints at the same time!
-## NOTE: The following constraints should be used with the XADC core when using these ports as analog inputs.
-#set_property -dict { PACKAGE_PIN B7    IOSTANDARD LVCMOS33 } [get_ports { vaux12_p }]; #IO_L2P_T0_AD12P_35 Sch=ad_p[12] ChipKit pin=A6
-#set_property -dict { PACKAGE_PIN B6    IOSTANDARD LVCMOS33 } [get_ports { vaux12_n }]; #IO_L2N_T0_AD12N_35 Sch=ad_n[12] ChipKit pin=A7
-#set_property -dict { PACKAGE_PIN E6    IOSTANDARD LVCMOS33 } [get_ports { vaux13_p }]; #IO_L5P_T0_AD13P_35 Sch=ad_p[13] ChipKit pin=A8
-#set_property -dict { PACKAGE_PIN E5    IOSTANDARD LVCMOS33 } [get_ports { vaux13_n }]; #IO_L5N_T0_AD13N_35 Sch=ad_n[13] ChipKit pin=A9
-#set_property -dict { PACKAGE_PIN A4    IOSTANDARD LVCMOS33 } [get_ports { vaux14_p }]; #IO_L8P_T1_AD14P_35 Sch=ad_p[14] ChipKit pin=A10
-#set_property -dict { PACKAGE_PIN A3    IOSTANDARD LVCMOS33 } [get_ports { vaux14_n }]; #IO_L8N_T1_AD14N_35 Sch=ad_n[14] ChipKit pin=A11
-## ChipKit Inner Analog Header - as Digital I/O
-## NOTE: The following constraints should be used when using the inner analog header ports as digital I/O.
-#set_property -dict { PACKAGE_PIN B7    IOSTANDARD LVCMOS33 } [get_ports { ck_a6  }]; #IO_L2P_T0_AD12P_35 Sch=ad_p[12]
-#set_property -dict { PACKAGE_PIN B6    IOSTANDARD LVCMOS33 } [get_ports { ck_a7  }]; #IO_L2N_T0_AD12N_35 Sch=ad_n[12]
-#set_property -dict { PACKAGE_PIN E6    IOSTANDARD LVCMOS33 } [get_ports { ck_a8  }]; #IO_L5P_T0_AD13P_35 Sch=ad_p[13]
-#set_property -dict { PACKAGE_PIN E5    IOSTANDARD LVCMOS33 } [get_ports { ck_a9  }]; #IO_L5N_T0_AD13N_35 Sch=ad_n[13]
-#set_property -dict { PACKAGE_PIN A4    IOSTANDARD LVCMOS33 } [get_ports { ck_a10 }]; #IO_L8P_T1_AD14P_35 Sch=ad_p[14]
-#set_property -dict { PACKAGE_PIN A3    IOSTANDARD LVCMOS33 } [get_ports { ck_a11 }]; #IO_L8N_T1_AD14N_35 Sch=ad_n[14]
-
-## ChipKit SPI
-#set_property -dict { PACKAGE_PIN G1    IOSTANDARD LVCMOS33 } [get_ports { ck_miso }]; #IO_L17N_T2_35 Sch=ck_miso
-#set_property -dict { PACKAGE_PIN H1    IOSTANDARD LVCMOS33 } [get_ports { ck_mosi }]; #IO_L17P_T2_35 Sch=ck_mosi
-#set_property -dict { PACKAGE_PIN F1    IOSTANDARD LVCMOS33 } [get_ports { ck_sck }]; #IO_L18P_T2_35 Sch=ck_sck
-#set_property -dict { PACKAGE_PIN C1    IOSTANDARD LVCMOS33 } [get_ports { ck_ss }]; #IO_L16N_T2_35 Sch=ck_ss
-
-## ChipKit I2C
-#set_property -dict { PACKAGE_PIN L18   IOSTANDARD LVCMOS33 } [get_ports { ck_scl }]; #IO_L4P_T0_D04_14 Sch=ck_scl
-#set_property -dict { PACKAGE_PIN M18   IOSTANDARD LVCMOS33 } [get_ports { ck_sda }]; #IO_L4N_T0_D05_14 Sch=ck_sda
-#set_property -dict { PACKAGE_PIN A14   IOSTANDARD LVCMOS33 } [get_ports { scl_pup }]; #IO_L9N_T1_DQS_AD3N_15 Sch=scl_pup
-#set_property -dict { PACKAGE_PIN A13   IOSTANDARD LVCMOS33 } [get_ports { sda_pup }]; #IO_L9P_T1_DQS_AD3P_15 Sch=sda_pup
-
-## Misc. ChipKit Ports
-#set_property -dict { PACKAGE_PIN M17   IOSTANDARD LVCMOS33 } [get_ports { ck_ioa }]; #IO_L10N_T1_D15_14 Sch=ck_ioa
-set_property -dict { PACKAGE_PIN C2    IOSTANDARD LVCMOS33 } [get_ports { IO_RST_N }]; #IO_L16P_T2_35 Sch=ck_rst
-
-## SMSC Ethernet PHY
-#set_property -dict { PACKAGE_PIN D17   IOSTANDARD LVCMOS33 } [get_ports { eth_col }]; #IO_L16N_T2_A27_15 Sch=eth_col
-#set_property -dict { PACKAGE_PIN G14   IOSTANDARD LVCMOS33 } [get_ports { eth_crs }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=eth_crs
-#set_property -dict { PACKAGE_PIN F16   IOSTANDARD LVCMOS33 } [get_ports { eth_mdc }]; #IO_L14N_T2_SRCC_15 Sch=eth_mdc
-#set_property -dict { PACKAGE_PIN K13   IOSTANDARD LVCMOS33 } [get_ports { eth_mdio }]; #IO_L17P_T2_A26_15 Sch=eth_mdio
-#set_property -dict { PACKAGE_PIN G18   IOSTANDARD LVCMOS33 } [get_ports { eth_ref_clk }]; #IO_L22P_T3_A17_15 Sch=eth_ref_clk
-#set_property -dict { PACKAGE_PIN C16   IOSTANDARD LVCMOS33 } [get_ports { eth_rstn }]; #IO_L20P_T3_A20_15 Sch=eth_rstn
-#set_property -dict { PACKAGE_PIN F15   IOSTANDARD LVCMOS33 } [get_ports { eth_rx_clk }]; #IO_L14P_T2_SRCC_15 Sch=eth_rx_clk
-#set_property -dict { PACKAGE_PIN G16   IOSTANDARD LVCMOS33 } [get_ports { eth_rx_dv }]; #IO_L13N_T2_MRCC_15 Sch=eth_rx_dv
-#set_property -dict { PACKAGE_PIN D18   IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[0] }]; #IO_L21N_T3_DQS_A18_15 Sch=eth_rxd[0]
-#set_property -dict { PACKAGE_PIN E17   IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[1] }]; #IO_L16P_T2_A28_15 Sch=eth_rxd[1]
-#set_property -dict { PACKAGE_PIN E18   IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[2] }]; #IO_L21P_T3_DQS_15 Sch=eth_rxd[2]
-#set_property -dict { PACKAGE_PIN G17   IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[3] }]; #IO_L18N_T2_A23_15 Sch=eth_rxd[3]
-#set_property -dict { PACKAGE_PIN C17   IOSTANDARD LVCMOS33 } [get_ports { eth_rxerr }]; #IO_L20N_T3_A19_15 Sch=eth_rxerr
-#set_property -dict { PACKAGE_PIN H16   IOSTANDARD LVCMOS33 } [get_ports { eth_tx_clk }]; #IO_L13P_T2_MRCC_15 Sch=eth_tx_clk
-#set_property -dict { PACKAGE_PIN H15   IOSTANDARD LVCMOS33 } [get_ports { eth_tx_en }]; #IO_L19N_T3_A21_VREF_15 Sch=eth_tx_en
-#set_property -dict { PACKAGE_PIN H14   IOSTANDARD LVCMOS33 } [get_ports { eth_txd[0] }]; #IO_L15P_T2_DQS_15 Sch=eth_txd[0]
-#set_property -dict { PACKAGE_PIN J14   IOSTANDARD LVCMOS33 } [get_ports { eth_txd[1] }]; #IO_L19P_T3_A22_15 Sch=eth_txd[1]
-#set_property -dict { PACKAGE_PIN J13   IOSTANDARD LVCMOS33 } [get_ports { eth_txd[2] }]; #IO_L17N_T2_A25_15 Sch=eth_txd[2]
-#set_property -dict { PACKAGE_PIN H17   IOSTANDARD LVCMOS33 } [get_ports { eth_txd[3] }]; #IO_L18P_T2_A24_15 Sch=eth_txd[3]
-
-## Quad SPI Flash
-#set_property -dict { PACKAGE_PIN L13   IOSTANDARD LVCMOS33 } [get_ports { qspi_cs }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_cs
-#set_property -dict { PACKAGE_PIN K17   IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0]
-#set_property -dict { PACKAGE_PIN K18   IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1]
-#set_property -dict { PACKAGE_PIN L14   IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2]
-#set_property -dict { PACKAGE_PIN M14   IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3]
-
-## Power Measurements
-#set_property -dict { PACKAGE_PIN B17   IOSTANDARD LVCMOS33     } [get_ports { vsnsvu_n }]; #IO_L7N_T1_AD2N_15 Sch=ad_n[2]
-#set_property -dict { PACKAGE_PIN B16   IOSTANDARD LVCMOS33     } [get_ports { vsnsvu_p }]; #IO_L7P_T1_AD2P_15 Sch=ad_p[2]
-#set_property -dict { PACKAGE_PIN B12   IOSTANDARD LVCMOS33     } [get_ports { vsns5v0_n }]; #IO_L3N_T0_DQS_AD1N_15 Sch=ad_n[1]
-#set_property -dict { PACKAGE_PIN C12   IOSTANDARD LVCMOS33     } [get_ports { vsns5v0_p }]; #IO_L3P_T0_DQS_AD1P_15 Sch=ad_p[1]
-#set_property -dict { PACKAGE_PIN F14   IOSTANDARD LVCMOS33     } [get_ports { isns5v0_n }]; #IO_L5N_T0_AD9N_15 Sch=ad_n[9]
-#set_property -dict { PACKAGE_PIN F13   IOSTANDARD LVCMOS33     } [get_ports { isns5v0_p }]; #IO_L5P_T0_AD9P_15 Sch=ad_p[9]
-#set_property -dict { PACKAGE_PIN A16   IOSTANDARD LVCMOS33     } [get_ports { isns0v95_n }]; #IO_L8N_T1_AD10N_15 Sch=ad_n[10]
-#set_property -dict { PACKAGE_PIN A15   IOSTANDARD LVCMOS33     } [get_ports { isns0v95_p }]; #IO_L8P_T1_AD10P_15 Sch=ad_p[10]
diff --git a/examples/fpga/artya7/rtl/top_artya7.sv b/examples/fpga/artya7/rtl/top_artya7.sv
deleted file mode 100644
index d6000a20..00000000
--- a/examples/fpga/artya7/rtl/top_artya7.sv
+++ /dev/null
@@ -1,145 +0,0 @@
-// Copyright lowRISC contributors.
-// Licensed under the Apache License, Version 2.0, see LICENSE for details.
-// SPDX-License-Identifier: Apache-2.0
-
-module top_artya7 (
-    input               IO_CLK,
-    input               IO_RST_N,
-    output [3:0]        LED
-);
-
-  parameter int          FPGAPowerAnalysis = 0;
-  // Choose 64kb memory for normal builds and 256kb for FPGAPowerAnalysis builds. The latter will
-  // not fit in the Arty A7-35 Board FPGA.
-  parameter int          MEM_SIZE          = FPGAPowerAnalysis == 0 ? 64 * 1024 : 256 * 1024;
-  parameter logic [31:0] MEM_START         = 32'h00000000;
-  parameter logic [31:0] MEM_MASK          = MEM_SIZE-1;
-  parameter              SRAMInitFile      = "";
-
-  logic clk_sys, rst_sys_n;
-
-  // Instruction connection to SRAM
-  logic        instr_req;
-  logic        instr_gnt;
-  logic        instr_rvalid;
-  logic [31:0] instr_addr;
-  logic [31:0] instr_rdata;
-
-  // Data connection to SRAM
-  logic        data_req;
-  logic        data_gnt;
-  logic        data_rvalid;
-  logic        data_we;
-  logic  [3:0] data_be;
-  logic [31:0] data_addr;
-  logic [31:0] data_wdata;
-  logic [31:0] data_rdata;
-
-  ibex_top #(
-     .RegFile(ibex_pkg::RegFileFPGA),
-     .DmHaltAddr(32'h00000000),
-     .DmExceptionAddr(32'h00000000)
-  ) u_top (
-     .clk_i                 (clk_sys),
-     .rst_ni                (rst_sys_n),
-
-     .test_en_i             ('b0),
-     .scan_rst_ni           (1'b1),
-     .ram_cfg_i             ('b0),
-
-     .hart_id_i             (32'b0),
-     // First instruction executed is at 0x0 + 0x80
-     .boot_addr_i           (32'h00000000),
-
-     .instr_req_o           (instr_req),
-     .instr_gnt_i           (instr_gnt),
-     .instr_rvalid_i        (instr_rvalid),
-     .instr_addr_o          (instr_addr),
-     .instr_rdata_i         (instr_rdata),
-     .instr_rdata_intg_i    ('0),
-     .instr_err_i           ('b0),
-
-     .data_req_o            (data_req),
-     .data_gnt_i            (data_gnt),
-     .data_rvalid_i         (data_rvalid),
-     .data_we_o             (data_we),
-     .data_be_o             (data_be),
-     .data_addr_o           (data_addr),
-     .data_wdata_o          (data_wdata),
-     .data_wdata_intg_o     (),
-     .data_rdata_i          (data_rdata),
-     .data_rdata_intg_i     ('0),
-     .data_err_i            ('b0),
-
-     .irq_software_i        (1'b0),
-     .irq_timer_i           (1'b0),
-     .irq_external_i        (1'b0),
-     .irq_fast_i            (15'b0),
-     .irq_nm_i              (1'b0),
-
-     .debug_req_i           ('b0),
-     .crash_dump_o          (),
-
-     .fetch_enable_i        ('b1),
-     .alert_minor_o         (),
-     .alert_major_internal_o(),
-     .alert_major_bus_o     (),
-     .core_sleep_o          ()
-  );
-
-  // SRAM block for instruction and data storage
-  ram_2p #(
-    .Depth(MEM_SIZE / 4),
-    .MemInitFile(SRAMInitFile)
-  ) u_ram (
-    .clk_i (clk_sys),
-    .rst_ni(rst_sys_n),
-
-    .a_req_i   (data_req),
-    .a_we_i    (data_we),
-    .a_be_i    (data_be),
-    .a_addr_i  (data_addr),
-    .a_wdata_i (data_wdata),
-    .a_rvalid_o(data_rvalid),
-    .a_rdata_o (data_rdata),
-
-    .b_req_i   (instr_req),
-    .b_we_i    (1'b0),
-    .b_be_i    (4'b0),
-    .b_addr_i  (instr_addr),
-    .b_wdata_i (32'b0),
-    .b_rvalid_o(instr_rvalid),
-    .b_rdata_o (instr_rdata)
-  );
-
-  assign instr_gnt = instr_req;
-  assign data_gnt  = data_req;
-
-  // Connect the LED output to the lower four bits of the most significant
-  // byte
-  logic [3:0] leds;
-  always_ff @(posedge clk_sys or negedge rst_sys_n) begin
-    if (!rst_sys_n) begin
-      leds <= 4'b0;
-    end else begin
-      if (data_req && data_we) begin
-        for (int i = 0; i < 4; i = i + 1) begin
-          if (data_be[i] == 1'b1) begin
-            leds <= data_wdata[i*8 +: 4];
-          end
-        end
-      end
-    end
-  end
-  assign LED = leds;
-
-  // Clock and reset
-  clkgen_xil7series
-    clkgen(
-      .IO_CLK,
-      .IO_RST_N,
-      .clk_sys,
-      .rst_sys_n
-    );
-
-endmodule
diff --git a/examples/fpga/artya7/top_artya7.core b/examples/fpga/artya7/top_artya7.core
deleted file mode 100644
index b30fed1c..00000000
--- a/examples/fpga/artya7/top_artya7.core
+++ /dev/null
@@ -1,64 +0,0 @@
-CAPI=2:
-# Copyright lowRISC contributors.
-# Licensed under the Apache License, Version 2.0, see LICENSE for details.
-# SPDX-License-Identifier: Apache-2.0
-name: "lowrisc:ibex:top_artya7:0.1"
-description: "Ibex example toplevel for Arty A7 boards (both, -35 and -100)"
-filesets:
-  files_rtl_artya7:
-    depend:
-      - lowrisc:ibex:ibex_top
-      - lowrisc:ibex:fpga_xilinx_shared
-    files:
-      - rtl/top_artya7.sv
-    file_type: systemVerilogSource
-
-  files_constraints:
-    files:
-      - data/pins_artya7.xdc
-    file_type: xdc
-
-  files_tcl:
-    files:
-      - util/vivado_setup_hooks.tcl : { file_type: tclSource }
-      - util/vivado_hook_write_bitstream_pre.tcl : { file_type: user, copyto: vivado_hook_write_bitstream_pre.tcl }
-
-parameters:
-  # XXX: This parameter needs to be absolute, or relative to the *.runs/synth_1
-  # directory. It's best to pass it as absolute path when invoking fusesoc, e.g.
-  # --SRAMInitFile=$PWD/sw/led/led.vmem
-  # XXX: The VMEM file should be added to the sources of the Vivado project to
-  # make the Vivado dependency tracking work. However this requires changes to
-  # fusesoc first.
-  SRAMInitFile:
-    datatype: str
-    description: SRAM initialization file in vmem hex format
-    default: "../../../../../examples/sw/led/led.vmem"
-    paramtype: vlogparam
-
-  # For value definition, please see ip/prim/rtl/prim_pkg.sv
-  PRIM_DEFAULT_IMPL:
-    datatype: str
-    paramtype: vlogdefine
-    description: Primitives implementation to use, e.g. "prim_pkg::ImplGeneric".
-
-  FPGAPowerAnalysis:
-    datatype: int
-    paramtype: vlogparam
-    description: Enables custom power analysis scripts for Vivado.
-
-targets:
-  synth:
-    default_tool: vivado
-    filesets:
-      - files_rtl_artya7
-      - files_constraints
-      - files_tcl
-    toplevel: top_artya7
-    parameters:
-      - SRAMInitFile
-      - PRIM_DEFAULT_IMPL=prim_pkg::ImplXilinx
-      - FPGAPowerAnalysis
-    tools:
-      vivado:
-        part: "xc7a100tcsg324-1"  # Default to Arty A7-100
diff --git a/examples/fpga/artya7/util/vivado_hook_write_bitstream_pre.tcl b/examples/fpga/artya7/util/vivado_hook_write_bitstream_pre.tcl
deleted file mode 100644
index 8f9f3614..00000000
--- a/examples/fpga/artya7/util/vivado_hook_write_bitstream_pre.tcl
+++ /dev/null
@@ -1,24 +0,0 @@
-open_project ../../lowrisc_ibex_top_artya7_0.1.xpr
-set saif_name "detailed_power.saif"
-
-open_run impl_1
-
-# Runs a post implementation functional simulation with the memory initialized with SRAMInitFile.
-# Feeds clock (100mhz) and reset switch and records switching activity for 3ms.
-set_property top top_artya7 [current_fileset sim_1]
-launch_simulation -mode post-implementation -type functional
-open_saif "$saif_name"
-log_saif [get_objects -r *]
-add_force {/top_artya7/IO_CLK} -radix bin {1 0ns} {0 5ns} -repeat_every 10ns
-add_force {/top_artya7/IO_RST_N} -radix bin {1 0ns}
-run 3ms
-close_saif
-
-
-# Reporting power using .saif generated above
-open_run impl_1
-set_operating_conditions -process maximum
-read_saif "../../lowrisc_ibex_top_artya7_0.1.sim/sim_1/impl/func/xsim/$saif_name" 
-read_saif "../../lowrisc_ibex_top_artya7_0.1.sim/sim_1/impl/func/xsim/$saif_name"  -strip_path top_artya7 
-set_units -power uW
-report_power -name {detailed_power_report} -verbose -file post_implementation_power_result.log -hierarchical_depth 20
diff --git a/examples/fpga/artya7/util/vivado_setup_hooks.tcl b/examples/fpga/artya7/util/vivado_setup_hooks.tcl
deleted file mode 100644
index d00ad006..00000000
--- a/examples/fpga/artya7/util/vivado_setup_hooks.tcl
+++ /dev/null
@@ -1,14 +0,0 @@
-# Copyright lowRISC contributors.
-# Licensed under the Apache License, Version 2.0, see LICENSE for details.
-# SPDX-License-Identifier: Apache-2.0
-
-# Setup hook scripts, to be called at various stages during the build process
-# See Xilinx UG 894 ("Using Tcl Scripting") for documentation.
-
-# fusesoc-generated workroot containing the Vivado project file
-set workroot [pwd]
-set vlogparam_list [get_property generic [get_filesets sources_1]]
-set FPGAPowerAnalysis [regexp {FPGAPowerAnalysis} $vlogparam_list]
-if {$FPGAPowerAnalysis == 1} {
-        set_property STEPS.WRITE_BITSTREAM.TCL.PRE "${workroot}/vivado_hook_write_bitstream_pre.tcl" [get_runs impl_1]
-}
diff --git a/examples/sw/led/Makefile b/examples/sw/led/Makefile
deleted file mode 100644
index fadd10ed..00000000
--- a/examples/sw/led/Makefile
+++ /dev/null
@@ -1,60 +0,0 @@
-# Copyright lowRISC contributors.
-# Licensed under the Apache License, Version 2.0, see LICENSE for details.
-# SPDX-License-Identifier: Apache-2.0
-#
-# Generate a baremetal application
-
-PROGRAM ?= led
-PROGRAM_CFLAGS = -Wall -g -Os
-ARCH = rv32imc
-# ARCH = rv32im # to disable compressed instructions
-SRCS = $(PROGRAM).c
-
-CC = riscv32-unknown-elf-gcc
-
-CROSS_COMPILE = $(patsubst %-gcc,%-,$(CC))
-OBJCOPY ?= $(CROSS_COMPILE)objcopy
-OBJDUMP ?= $(CROSS_COMPILE)objdump
-
-LINKER_SCRIPT ?= link.ld
-CRT ?= crt0.S
-CFLAGS ?= -march=$(ARCH) -mabi=ilp32 -static -mcmodel=medany \
-	-fvisibility=hidden -nostdlib -nostartfiles $(PROGRAM_CFLAGS)
-
-OBJS := ${SRCS:.c=.o} ${CRT:.S=.o}
-DEPS = $(OBJS:%.o=%.d)
-
-OUTFILES = $(PROGRAM).elf $(PROGRAM).vmem $(PROGRAM).bin $(PROGRAM).dis
-
-all: $(OUTFILES)
-
-$(PROGRAM).elf: $(OBJS) $(LINKER_SCRIPT)
-	$(CC) $(CFLAGS) -T $(LINKER_SCRIPT) $(OBJS) -o $@ $(LIBS)
-
-%.dis: %.elf
-	$(OBJDUMP) -SD $^ > $@
-
-# Note: this target requires the srecord package to be installed.
-# XXX: This could be replaced by objcopy once
-# https://sourceware.org/bugzilla/show_bug.cgi?id=19921
-# is widely available.
-# XXX: Currently the start address 0x00000000 is hardcoded. It could/should be
-# read from the elf file, but is lost in the bin file.
-# Switching to objcopy will resolve that as well.
-%.vmem: %.bin
-	srec_cat $^ -binary -offset 0x0000 -byte-swap 4 -o $@ -vmem
-
-%.bin: %.elf
-	$(OBJCOPY) -O binary $^ $@
-
-%.o: %.c
-	$(CC) $(CFLAGS) -MMD -c $(INCS) -o $@ $<
-
-%.o: %.S
-	$(CC) $(CFLAGS) -MMD -c $(INCS) -o $@ $<
-
-clean:
-	$(RM) -f *.o *.d
-
-distclean: clean
-	$(RM) -f $(OUTFILES)
diff --git a/examples/sw/led/crt0.S b/examples/sw/led/crt0.S
deleted file mode 100644
index 9f987f7e..00000000
--- a/examples/sw/led/crt0.S
+++ /dev/null
@@ -1,89 +0,0 @@
-  .section .text
-
-default_exc_handler:
-  jal x0, default_exc_handler
-
-reset_handler:
-  /* set all registers to zero */
-  mv  x1, x0
-  mv  x2, x1
-  mv  x3, x1
-  mv  x4, x1
-  mv  x5, x1
-  mv  x6, x1
-  mv  x7, x1
-  mv  x8, x1
-  mv  x9, x1
-  mv x10, x1
-  mv x11, x1
-  mv x12, x1
-  mv x13, x1
-  mv x14, x1
-  mv x15, x1
-  mv x16, x1
-  mv x17, x1
-  mv x18, x1
-  mv x19, x1
-  mv x20, x1
-  mv x21, x1
-  mv x22, x1
-  mv x23, x1
-  mv x24, x1
-  mv x25, x1
-  mv x26, x1
-  mv x27, x1
-  mv x28, x1
-  mv x29, x1
-  mv x30, x1
-  mv x31, x1
-
-  /* stack initilization */
-  la   x2, _stack_start
-
-_start:
-  .global _start
-
-  /* clear BSS */
-  la x26, _bss_start
-  la x27, _bss_end
-
-  bge x26, x27, zero_loop_end
-
-zero_loop:
-  sw x0, 0(x26)
-  addi x26, x26, 4
-  ble x26, x27, zero_loop
-zero_loop_end:
-
-
-main_entry:
-  /* jump to main program entry point (argc = argv = 0) */
-  addi x10, x0, 0
-  addi x11, x0, 0
-  jal x1, main
-
-/* =================================================== [ exceptions ] === */
-/* This section has to be down here, since we have to disable rvc for it  */
-
-  .section .vectors, "ax"
-  .option norvc;
-
-  // external interrupts are handled by the same callback
-  // until compiler supports IRQ routines
-  .org 0x00
-  .rept 31
-  nop
-  .endr
-  jal x0, default_exc_handler
-
-  // reset vector
-  .org 0x80
-  jal x0, reset_handler
-
-  // illegal instruction exception
-  .org 0x84
-  jal x0, default_exc_handler
-
-  // ecall handler
-  .org 0x88
-  jal x0, default_exc_handler
diff --git a/examples/sw/led/led.c b/examples/sw/led/led.c
deleted file mode 100644
index ca72c78c..00000000
--- a/examples/sw/led/led.c
+++ /dev/null
@@ -1,47 +0,0 @@
-// Copyright lowRISC contributors.
-// Licensed under the Apache License, Version 2.0, see LICENSE for details.
-// SPDX-License-Identifier: Apache-2.0
-
-#include <stdint.h>
-#define CLK_FIXED_FREQ_HZ (50ULL * 1000 * 1000)
-
-/**
- * Delay loop executing within 8 cycles on ibex
- */
-static void delay_loop_ibex(unsigned long loops) {
-  int out; /* only to notify compiler of modifications to |loops| */
-  asm volatile(
-      "1: nop             \n" // 1 cycle
-      "   nop             \n" // 1 cycle
-      "   nop             \n" // 1 cycle
-      "   nop             \n" // 1 cycle
-      "   addi %1, %1, -1 \n" // 1 cycle
-      "   bnez %1, 1b     \n" // 3 cycles
-      : "=&r" (out)
-      : "0" (loops)
-  );
-}
-
-static int usleep_ibex(unsigned long usec) {
-  unsigned long usec_cycles;
-  usec_cycles = CLK_FIXED_FREQ_HZ * usec / 1000 / 1000 / 8;
-
-  delay_loop_ibex(usec_cycles);
-  return 0;
-}
-
-static int usleep(unsigned long usec) {
-  return usleep_ibex(usec);
-}
-
-int main(int argc, char **argv) {
-  // The lowest four bits of the highest byte written to the memory region named
-  // "stack" are connected to the LEDs of the board.
-  volatile uint8_t *var = (volatile uint8_t *) 0x0000c010;
-  *var = 0x0a;
-
-  while (1) {
-    usleep(1000 * 1000); // 1000 ms
-    *var = ~(*var);
-  }
-}
diff --git a/examples/sw/led/link.ld b/examples/sw/led/link.ld
deleted file mode 100644
index 1b7fef15..00000000
--- a/examples/sw/led/link.ld
+++ /dev/null
@@ -1,105 +0,0 @@
-OUTPUT_ARCH(riscv)
-
-/* required to correctly link newlib */
-GROUP( -lc -lgloss -lgcc -lsupc++ )
-
-SEARCH_DIR(.)
-__DYNAMIC  =  0;
-
-MEMORY
-{
-    rom         : ORIGIN = 0x00000000, LENGTH = 0xC000 /* 48 kB */
-    stack       : ORIGIN = 0x0000C000, LENGTH = 0x4000 /* 16 kB */
-}
-
-/* Stack information variables */
-_min_stack      = 0x2000;   /* 8K - minimum stack space to reserve */
-_stack_len     = LENGTH(stack);
-_stack_start   = ORIGIN(stack) + LENGTH(stack);
-
-/* We have to align each sector to word boundaries as our current s19->slm
- * conversion scripts are not able to handle non-word aligned sections. */
-
-SECTIONS
-{
-    .vectors :
-    {
-        . = ALIGN(4);
-        KEEP(*(.vectors))
-    } > rom
-
-    .text : {
-        . = ALIGN(4);
-        _stext = .;
-        *(.text)
-        *(.text.*)
-        _etext  =  .;
-        __CTOR_LIST__ = .;
-        LONG((__CTOR_END__ - __CTOR_LIST__) / 4 - 2)
-        *(.ctors)
-        LONG(0)
-        __CTOR_END__ = .;
-        __DTOR_LIST__ = .;
-        LONG((__DTOR_END__ - __DTOR_LIST__) / 4 - 2)
-        *(.dtors)
-        LONG(0)
-        __DTOR_END__ = .;
-        *(.lit)
-        *(.shdata)
-        . = ALIGN(4);
-        _endtext = .;
-    }  > rom
-
-    .rodata : {
-        . = ALIGN(4);
-        *(.rodata);
-        *(.rodata.*)
-    } > rom
-
-    .shbss :
-    {
-        . = ALIGN(4);
-        *(.shbss)
-    } > rom
-
-    .data : {
-        . = ALIGN(4);
-        sdata  =  .;
-        _sdata  =  .;
-        *(.data);
-        *(.data.*)
-        edata  =  .;
-        _edata  =  .;
-    } > rom
-
-    .bss :
-    {
-        . = ALIGN(4);
-        _bss_start = .;
-        *(.bss)
-        *(.bss.*)
-        *(.sbss)
-        *(.sbss.*)
-        *(COMMON)
-        _bss_end = .;
-    } > rom
-
-    /* ensure there is enough room for stack */
-    .stack (NOLOAD): {
-        . = ALIGN(4);
-        . = . + _min_stack ;
-        . = ALIGN(4);
-        stack = . ;
-        _stack = . ;
-    } > stack
-
-    .stab  0 (NOLOAD) :
-    {
-        [ .stab ]
-    }
-
-    .stabstr  0 (NOLOAD) :
-    {
-        [ .stabstr ]
-    }
-}