diff --git a/dv/riscv_compliance/ibex_riscv_compliance.core b/dv/riscv_compliance/ibex_riscv_compliance.core
index f68a80d3..68641206 100644
--- a/dv/riscv_compliance/ibex_riscv_compliance.core
+++ b/dv/riscv_compliance/ibex_riscv_compliance.core
@@ -64,6 +64,7 @@ targets:
     parameters:
       - RV32M
       - RV32E
+      - RV32B
       - MultiplierImplementation
       - BranchTargetALU
       - WritebackStage
diff --git a/ibex_core_tracing.core b/ibex_core_tracing.core
index a0f315fb..53c3815b 100644
--- a/ibex_core_tracing.core
+++ b/ibex_core_tracing.core
@@ -103,6 +103,7 @@ targets:
       - SYNTHESIS=true
       - RV32M
       - RV32E
+      - RV32B
       - BranchTargetALU
       - WritebackStage
       - MultiplierImplementation