diff --git a/doc/performance_counters.rst b/doc/performance_counters.rst
index e42b32b8..9834264f 100644
--- a/doc/performance_counters.rst
+++ b/doc/performance_counters.rst
@@ -9,6 +9,7 @@ The performance counters are placed inside the Control and Status Registers (CSR
 Ibex implements the clock cycle counter ``mcycle(h)``, the retired instruction counter ``minstret(h)``, as well as the 29 event counters ``mhpmcounter3(h)`` - ``mhpmcounter31(h)`` and the corresponding event selector CSRs ``mhpmevent3`` - ``mhpmevent31``, and the ``mcountinhibit`` CSR to individually enable/disable the counters.
 ``mcycle(h)`` and ``minstret(h)`` are always available and 64 bit wide.
 The ``mhpmcounter`` performance counters are optional (unavailable by default) and parametrizable in width.
+To ensure that the ``mhpmcounter`` registers are optimized away when not required, some synthesis tools might need extra settings (e.g. increasing the "effort" to high).
 
 Event Selector
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