diff --git a/dv/uvm/core_ibex/riscv_dv_extension/testlist.yaml b/dv/uvm/core_ibex/riscv_dv_extension/testlist.yaml
index 63257722..847a191a 100644
--- a/dv/uvm/core_ibex/riscv_dv_extension/testlist.yaml
+++ b/dv/uvm/core_ibex/riscv_dv_extension/testlist.yaml
@@ -582,5 +582,8 @@
   gen_test: riscv_rand_instr_test
   gen_opts: >
     +instr_cnt=6000
-    +num_of_sub_program=2
+    +pmp_randomize=0
+    +pmp_allow_addr_overlap=0
+    +pmp_max_offset=00021000
+    +boot_mode=u
   rtl_test: core_ibex_base_test
diff --git a/dv/uvm/core_ibex/yaml/rtl_simulation.yaml b/dv/uvm/core_ibex/yaml/rtl_simulation.yaml
index 64224368..7198bd7f 100644
--- a/dv/uvm/core_ibex/yaml/rtl_simulation.yaml
+++ b/dv/uvm/core_ibex/yaml/rtl_simulation.yaml
@@ -24,7 +24,7 @@
          -Mdir=<out>/vcs_simv.csrc
          -o <out>/vcs_simv
          -debug_access+pp
-         -lca -kdb <wave_opts> <cov_opts>"
+         -lca -kdb <cmp_opts> <wave_opts> <cov_opts>"
     cov_opts: >
       -cm line+tgl+assert+fsm+branch
       -cm_tgl portsonly