diff --git a/rtl/ibex_pkg.sv b/rtl/ibex_pkg.sv index 6d60ed27..6d568214 100644 --- a/rtl/ibex_pkg.sv +++ b/rtl/ibex_pkg.sv @@ -8,565 +8,565 @@ */ package ibex_pkg; -//////////////// -// IO Structs // -//////////////// - -typedef struct packed { - logic [31:0] current_pc; - logic [31:0] next_pc; - logic [31:0] last_data_addr; - logic [31:0] exception_addr; -} crash_dump_t; - -typedef struct packed { - logic dummy_instr_id; - logic [4:0] raddr_a; - logic [4:0] waddr_a; - logic we_a; - logic [4:0] raddr_b; -} core2rf_t; - -///////////////////// -// Parameter Enums // -///////////////////// - -typedef enum integer { - RegFileFF = 0, - RegFileFPGA = 1, - RegFileLatch = 2 -} regfile_e; - -typedef enum integer { - RV32MNone = 0, - RV32MSlow = 1, - RV32MFast = 2, - RV32MSingleCycle = 3 -} rv32m_e; - -typedef enum integer { - RV32BNone = 0, - RV32BBalanced = 1, - RV32BFull = 2 -} rv32b_e; - -///////////// -// Opcodes // -///////////// - -typedef enum logic [6:0] { - OPCODE_LOAD = 7'h03, - OPCODE_MISC_MEM = 7'h0f, - OPCODE_OP_IMM = 7'h13, - OPCODE_AUIPC = 7'h17, - OPCODE_STORE = 7'h23, - OPCODE_OP = 7'h33, - OPCODE_LUI = 7'h37, - OPCODE_BRANCH = 7'h63, - OPCODE_JALR = 7'h67, - OPCODE_JAL = 7'h6f, - OPCODE_SYSTEM = 7'h73 -} opcode_e; - - -//////////////////// -// ALU operations // -//////////////////// - -typedef enum logic [5:0] { - // Arithmetics - ALU_ADD, - ALU_SUB, - - // Logics - ALU_XOR, - ALU_OR, - ALU_AND, - // RV32B - ALU_XNOR, - ALU_ORN, - ALU_ANDN, - - // Shifts - ALU_SRA, - ALU_SRL, - ALU_SLL, - // RV32B - ALU_SRO, - ALU_SLO, - ALU_ROR, - ALU_ROL, - ALU_GREV, - ALU_GORC, - ALU_SHFL, - ALU_UNSHFL, - - // Comparisons - ALU_LT, - ALU_LTU, - ALU_GE, - ALU_GEU, - ALU_EQ, - ALU_NE, - // RV32B - ALU_MIN, - ALU_MINU, - ALU_MAX, - ALU_MAXU, - - // Pack - // RV32B - ALU_PACK, - ALU_PACKU, - ALU_PACKH, - - // Sign-Extend - // RV32B - ALU_SEXTB, - ALU_SEXTH, - - // Bitcounting - // RV32B - ALU_CLZ, - ALU_CTZ, - ALU_PCNT, - - // Set lower than - ALU_SLT, - ALU_SLTU, - - // Ternary Bitmanip Operations - // RV32B - ALU_CMOV, - ALU_CMIX, - ALU_FSL, - ALU_FSR, - - // Single-Bit Operations - // RV32B - ALU_SBSET, - ALU_SBCLR, - ALU_SBINV, - ALU_SBEXT, - - // Bit Extract / Deposit - // RV32B - ALU_BEXT, - ALU_BDEP, - - // Bit Field Place - // RV32B - ALU_BFP, - - // Carry-less Multiply - // RV32B - ALU_CLMUL, - ALU_CLMULR, - ALU_CLMULH, - - // Cyclic Redundancy Check - ALU_CRC32_B, - ALU_CRC32C_B, - ALU_CRC32_H, - ALU_CRC32C_H, - ALU_CRC32_W, - ALU_CRC32C_W -} alu_op_e; - -typedef enum logic [1:0] { - // Multiplier/divider - MD_OP_MULL, - MD_OP_MULH, - MD_OP_DIV, - MD_OP_REM -} md_op_e; - - -////////////////////////////////// -// Control and status registers // -////////////////////////////////// - -// CSR operations -typedef enum logic [1:0] { - CSR_OP_READ, - CSR_OP_WRITE, - CSR_OP_SET, - CSR_OP_CLEAR -} csr_op_e; - -// Privileged mode -typedef enum logic[1:0] { - PRIV_LVL_M = 2'b11, - PRIV_LVL_H = 2'b10, - PRIV_LVL_S = 2'b01, - PRIV_LVL_U = 2'b00 -} priv_lvl_e; - -// Constants for the dcsr.xdebugver fields -typedef enum logic[3:0] { - XDEBUGVER_NO = 4'd0, // no external debug support - XDEBUGVER_STD = 4'd4, // external debug according to RISC-V debug spec - XDEBUGVER_NONSTD = 4'd15 // debug not conforming to RISC-V debug spec -} x_debug_ver_e; - -////////////// -// WB stage // -////////////// - -// Type of instruction present in writeback stage -typedef enum logic[1:0] { - WB_INSTR_LOAD, // Instruction is awaiting load data - WB_INSTR_STORE, // Instruction is awaiting store response - WB_INSTR_OTHER // Instruction doesn't fit into above categories -} wb_instr_type_e; - -////////////// -// ID stage // -////////////// - -// Operand a selection -typedef enum logic[1:0] { - OP_A_REG_A, - OP_A_FWD, - OP_A_CURRPC, - OP_A_IMM -} op_a_sel_e; - -// Immediate a selection -typedef enum logic { - IMM_A_Z, - IMM_A_ZERO -} imm_a_sel_e; - -// Operand b selection -typedef enum logic { - OP_B_REG_B, - OP_B_IMM -} op_b_sel_e; - -// Immediate b selection -typedef enum logic [2:0] { - IMM_B_I, - IMM_B_S, - IMM_B_B, - IMM_B_U, - IMM_B_J, - IMM_B_INCR_PC, - IMM_B_INCR_ADDR -} imm_b_sel_e; - -// Regfile write data selection -typedef enum logic { - RF_WD_EX, - RF_WD_CSR -} rf_wd_sel_e; - -////////////// -// IF stage // -////////////// - -// PC mux selection -typedef enum logic [2:0] { - PC_BOOT, - PC_JUMP, - PC_EXC, - PC_ERET, - PC_DRET, - PC_BP -} pc_sel_e; - -// Exception PC mux selection -typedef enum logic [1:0] { - EXC_PC_EXC, - EXC_PC_IRQ, - EXC_PC_DBD, - EXC_PC_DBG_EXC // Exception while in debug mode -} exc_pc_sel_e; - -// Interrupt requests -typedef struct packed { - logic irq_software; - logic irq_timer; - logic irq_external; - logic [14:0] irq_fast; // 15 fast interrupts, - // one interrupt is reserved for NMI (not visible through mip/mie) -} irqs_t; - -// Exception cause -typedef enum logic [5:0] { - EXC_CAUSE_IRQ_SOFTWARE_M = {1'b1, 5'd03}, - EXC_CAUSE_IRQ_TIMER_M = {1'b1, 5'd07}, - EXC_CAUSE_IRQ_EXTERNAL_M = {1'b1, 5'd11}, - // EXC_CAUSE_IRQ_FAST_0 = {1'b1, 5'd16}, - // EXC_CAUSE_IRQ_FAST_14 = {1'b1, 5'd30}, - EXC_CAUSE_IRQ_NM = {1'b1, 5'd31}, // == EXC_CAUSE_IRQ_FAST_15 - EXC_CAUSE_INSN_ADDR_MISA = {1'b0, 5'd00}, - EXC_CAUSE_INSTR_ACCESS_FAULT = {1'b0, 5'd01}, - EXC_CAUSE_ILLEGAL_INSN = {1'b0, 5'd02}, - EXC_CAUSE_BREAKPOINT = {1'b0, 5'd03}, - EXC_CAUSE_LOAD_ACCESS_FAULT = {1'b0, 5'd05}, - EXC_CAUSE_STORE_ACCESS_FAULT = {1'b0, 5'd07}, - EXC_CAUSE_ECALL_UMODE = {1'b0, 5'd08}, - EXC_CAUSE_ECALL_MMODE = {1'b0, 5'd11} -} exc_cause_e; - -// Debug cause -typedef enum logic [2:0] { - DBG_CAUSE_NONE = 3'h0, - DBG_CAUSE_EBREAK = 3'h1, - DBG_CAUSE_TRIGGER = 3'h2, - DBG_CAUSE_HALTREQ = 3'h3, - DBG_CAUSE_STEP = 3'h4 -} dbg_cause_e; - -// ICache constants -parameter int unsigned ADDR_W = 32; -parameter int unsigned BUS_SIZE = 32; -parameter int unsigned BUS_BYTES = BUS_SIZE/8; -parameter int unsigned BUS_W = $clog2(BUS_BYTES); -parameter int unsigned IC_SIZE_BYTES = 4096; -parameter int unsigned IC_NUM_WAYS = 2; -parameter int unsigned IC_LINE_SIZE = 64; -parameter int unsigned IC_LINE_BYTES = IC_LINE_SIZE/8; -parameter int unsigned IC_LINE_W = $clog2(IC_LINE_BYTES); -parameter int unsigned IC_NUM_LINES = IC_SIZE_BYTES / IC_NUM_WAYS / IC_LINE_BYTES; -parameter int unsigned IC_LINE_BEATS = IC_LINE_BYTES / BUS_BYTES; -parameter int unsigned IC_LINE_BEATS_W = $clog2(IC_LINE_BEATS); -parameter int unsigned IC_INDEX_W = $clog2(IC_NUM_LINES); -parameter int unsigned IC_INDEX_HI = IC_INDEX_W + IC_LINE_W - 1; -parameter int unsigned IC_TAG_SIZE = ADDR_W - IC_INDEX_W - IC_LINE_W + 1; // 1 valid bit -parameter int unsigned IC_OUTPUT_BEATS = (BUS_BYTES / 2); // number of halfwords - -// PMP constants -parameter int unsigned PMP_MAX_REGIONS = 16; -parameter int unsigned PMP_CFG_W = 8; - -// PMP acces type -parameter int unsigned PMP_I = 0; -parameter int unsigned PMP_D = 1; - -typedef enum logic [1:0] { - PMP_ACC_EXEC = 2'b00, - PMP_ACC_WRITE = 2'b01, - PMP_ACC_READ = 2'b10 -} pmp_req_e; - -// PMP cfg structures -typedef enum logic [1:0] { - PMP_MODE_OFF = 2'b00, - PMP_MODE_TOR = 2'b01, - PMP_MODE_NA4 = 2'b10, - PMP_MODE_NAPOT = 2'b11 -} pmp_cfg_mode_e; - -typedef struct packed { - logic lock; - pmp_cfg_mode_e mode; - logic exec; - logic write; - logic read; -} pmp_cfg_t; - -// Machine Security Configuration (ePMP) -typedef struct packed { - logic rlb; // Rule Locking Bypass - logic mmwp; // Machine Mode Whitelist Policy - logic mml; // Machine Mode Lockdown -} pmp_mseccfg_t; - -// CSRs -typedef enum logic[11:0] { - // Machine information - CSR_MHARTID = 12'hF14, - - // Machine trap setup - CSR_MSTATUS = 12'h300, - CSR_MISA = 12'h301, - CSR_MIE = 12'h304, - CSR_MTVEC = 12'h305, - CSR_MCOUNTEREN= 12'h306, - - // Machine trap handling - CSR_MSCRATCH = 12'h340, - CSR_MEPC = 12'h341, - CSR_MCAUSE = 12'h342, - CSR_MTVAL = 12'h343, - CSR_MIP = 12'h344, - - // Physical memory protection - CSR_PMPCFG0 = 12'h3A0, - CSR_PMPCFG1 = 12'h3A1, - CSR_PMPCFG2 = 12'h3A2, - CSR_PMPCFG3 = 12'h3A3, - CSR_PMPADDR0 = 12'h3B0, - CSR_PMPADDR1 = 12'h3B1, - CSR_PMPADDR2 = 12'h3B2, - CSR_PMPADDR3 = 12'h3B3, - CSR_PMPADDR4 = 12'h3B4, - CSR_PMPADDR5 = 12'h3B5, - CSR_PMPADDR6 = 12'h3B6, - CSR_PMPADDR7 = 12'h3B7, - CSR_PMPADDR8 = 12'h3B8, - CSR_PMPADDR9 = 12'h3B9, - CSR_PMPADDR10 = 12'h3BA, - CSR_PMPADDR11 = 12'h3BB, - CSR_PMPADDR12 = 12'h3BC, - CSR_PMPADDR13 = 12'h3BD, - CSR_PMPADDR14 = 12'h3BE, - CSR_PMPADDR15 = 12'h3BF, - - // ePMP control - CSR_MSECCFG = 12'h747, - CSR_MSECCFGH = 12'h757, - - // Debug trigger - CSR_TSELECT = 12'h7A0, - CSR_TDATA1 = 12'h7A1, - CSR_TDATA2 = 12'h7A2, - CSR_TDATA3 = 12'h7A3, - CSR_MCONTEXT = 12'h7A8, - CSR_SCONTEXT = 12'h7AA, - - // Debug/trace - CSR_DCSR = 12'h7b0, - CSR_DPC = 12'h7b1, - - // Debug - CSR_DSCRATCH0 = 12'h7b2, // optional - CSR_DSCRATCH1 = 12'h7b3, // optional - - // Machine Counter/Timers - CSR_MCOUNTINHIBIT = 12'h320, - CSR_MHPMEVENT3 = 12'h323, - CSR_MHPMEVENT4 = 12'h324, - CSR_MHPMEVENT5 = 12'h325, - CSR_MHPMEVENT6 = 12'h326, - CSR_MHPMEVENT7 = 12'h327, - CSR_MHPMEVENT8 = 12'h328, - CSR_MHPMEVENT9 = 12'h329, - CSR_MHPMEVENT10 = 12'h32A, - CSR_MHPMEVENT11 = 12'h32B, - CSR_MHPMEVENT12 = 12'h32C, - CSR_MHPMEVENT13 = 12'h32D, - CSR_MHPMEVENT14 = 12'h32E, - CSR_MHPMEVENT15 = 12'h32F, - CSR_MHPMEVENT16 = 12'h330, - CSR_MHPMEVENT17 = 12'h331, - CSR_MHPMEVENT18 = 12'h332, - CSR_MHPMEVENT19 = 12'h333, - CSR_MHPMEVENT20 = 12'h334, - CSR_MHPMEVENT21 = 12'h335, - CSR_MHPMEVENT22 = 12'h336, - CSR_MHPMEVENT23 = 12'h337, - CSR_MHPMEVENT24 = 12'h338, - CSR_MHPMEVENT25 = 12'h339, - CSR_MHPMEVENT26 = 12'h33A, - CSR_MHPMEVENT27 = 12'h33B, - CSR_MHPMEVENT28 = 12'h33C, - CSR_MHPMEVENT29 = 12'h33D, - CSR_MHPMEVENT30 = 12'h33E, - CSR_MHPMEVENT31 = 12'h33F, - CSR_MCYCLE = 12'hB00, - CSR_MINSTRET = 12'hB02, - CSR_MHPMCOUNTER3 = 12'hB03, - CSR_MHPMCOUNTER4 = 12'hB04, - CSR_MHPMCOUNTER5 = 12'hB05, - CSR_MHPMCOUNTER6 = 12'hB06, - CSR_MHPMCOUNTER7 = 12'hB07, - CSR_MHPMCOUNTER8 = 12'hB08, - CSR_MHPMCOUNTER9 = 12'hB09, - CSR_MHPMCOUNTER10 = 12'hB0A, - CSR_MHPMCOUNTER11 = 12'hB0B, - CSR_MHPMCOUNTER12 = 12'hB0C, - CSR_MHPMCOUNTER13 = 12'hB0D, - CSR_MHPMCOUNTER14 = 12'hB0E, - CSR_MHPMCOUNTER15 = 12'hB0F, - CSR_MHPMCOUNTER16 = 12'hB10, - CSR_MHPMCOUNTER17 = 12'hB11, - CSR_MHPMCOUNTER18 = 12'hB12, - CSR_MHPMCOUNTER19 = 12'hB13, - CSR_MHPMCOUNTER20 = 12'hB14, - CSR_MHPMCOUNTER21 = 12'hB15, - CSR_MHPMCOUNTER22 = 12'hB16, - CSR_MHPMCOUNTER23 = 12'hB17, - CSR_MHPMCOUNTER24 = 12'hB18, - CSR_MHPMCOUNTER25 = 12'hB19, - CSR_MHPMCOUNTER26 = 12'hB1A, - CSR_MHPMCOUNTER27 = 12'hB1B, - CSR_MHPMCOUNTER28 = 12'hB1C, - CSR_MHPMCOUNTER29 = 12'hB1D, - CSR_MHPMCOUNTER30 = 12'hB1E, - CSR_MHPMCOUNTER31 = 12'hB1F, - CSR_MCYCLEH = 12'hB80, - CSR_MINSTRETH = 12'hB82, - CSR_MHPMCOUNTER3H = 12'hB83, - CSR_MHPMCOUNTER4H = 12'hB84, - CSR_MHPMCOUNTER5H = 12'hB85, - CSR_MHPMCOUNTER6H = 12'hB86, - CSR_MHPMCOUNTER7H = 12'hB87, - CSR_MHPMCOUNTER8H = 12'hB88, - CSR_MHPMCOUNTER9H = 12'hB89, - CSR_MHPMCOUNTER10H = 12'hB8A, - CSR_MHPMCOUNTER11H = 12'hB8B, - CSR_MHPMCOUNTER12H = 12'hB8C, - CSR_MHPMCOUNTER13H = 12'hB8D, - CSR_MHPMCOUNTER14H = 12'hB8E, - CSR_MHPMCOUNTER15H = 12'hB8F, - CSR_MHPMCOUNTER16H = 12'hB90, - CSR_MHPMCOUNTER17H = 12'hB91, - CSR_MHPMCOUNTER18H = 12'hB92, - CSR_MHPMCOUNTER19H = 12'hB93, - CSR_MHPMCOUNTER20H = 12'hB94, - CSR_MHPMCOUNTER21H = 12'hB95, - CSR_MHPMCOUNTER22H = 12'hB96, - CSR_MHPMCOUNTER23H = 12'hB97, - CSR_MHPMCOUNTER24H = 12'hB98, - CSR_MHPMCOUNTER25H = 12'hB99, - CSR_MHPMCOUNTER26H = 12'hB9A, - CSR_MHPMCOUNTER27H = 12'hB9B, - CSR_MHPMCOUNTER28H = 12'hB9C, - CSR_MHPMCOUNTER29H = 12'hB9D, - CSR_MHPMCOUNTER30H = 12'hB9E, - CSR_MHPMCOUNTER31H = 12'hB9F, - CSR_CPUCTRL = 12'h7C0, - CSR_SECURESEED = 12'h7C1 -} csr_num_e; - -// CSR pmp-related offsets -parameter logic [11:0] CSR_OFF_PMP_CFG = 12'h3A0; // pmp_cfg @ 12'h3a0 - 12'h3a3 -parameter logic [11:0] CSR_OFF_PMP_ADDR = 12'h3B0; // pmp_addr @ 12'h3b0 - 12'h3bf - -// CSR status bits -parameter int unsigned CSR_MSTATUS_MIE_BIT = 3; -parameter int unsigned CSR_MSTATUS_MPIE_BIT = 7; -parameter int unsigned CSR_MSTATUS_MPP_BIT_LOW = 11; -parameter int unsigned CSR_MSTATUS_MPP_BIT_HIGH = 12; -parameter int unsigned CSR_MSTATUS_MPRV_BIT = 17; -parameter int unsigned CSR_MSTATUS_TW_BIT = 21; - -// CSR machine ISA -parameter logic [1:0] CSR_MISA_MXL = 2'd1; // M-XLEN: XLEN in M-Mode for RV32 - -// CSR interrupt pending/enable bits -parameter int unsigned CSR_MSIX_BIT = 3; -parameter int unsigned CSR_MTIX_BIT = 7; -parameter int unsigned CSR_MEIX_BIT = 11; -parameter int unsigned CSR_MFIX_BIT_LOW = 16; -parameter int unsigned CSR_MFIX_BIT_HIGH = 30; - -// CSR Machine Security Configuration bits -parameter int unsigned CSR_MSECCFG_MML_BIT = 0; -parameter int unsigned CSR_MSECCFG_MMWP_BIT = 1; -parameter int unsigned CSR_MSECCFG_RLB_BIT = 2; - -// These LFSR parameters have been generated with -// $ opentitan/util/design/gen-lfsr-seed.py --width 32 --seed 2480124384 --prefix "" -parameter int LfsrWidth = 32; -typedef logic [LfsrWidth-1:0] lfsr_seed_t; -typedef logic [LfsrWidth-1:0][$clog2(LfsrWidth)-1:0] lfsr_perm_t; -parameter lfsr_seed_t RndCnstLfsrSeedDefault = 32'hac533bf4; -parameter lfsr_perm_t RndCnstLfsrPermDefault = { - 160'h1e35ecba467fd1b12e958152c04fa43878a8daed -}; + //////////////// + // IO Structs // + //////////////// + + typedef struct packed { + logic [31:0] current_pc; + logic [31:0] next_pc; + logic [31:0] last_data_addr; + logic [31:0] exception_addr; + } crash_dump_t; + + typedef struct packed { + logic dummy_instr_id; + logic [4:0] raddr_a; + logic [4:0] waddr_a; + logic we_a; + logic [4:0] raddr_b; + } core2rf_t; + + ///////////////////// + // Parameter Enums // + ///////////////////// + + typedef enum integer { + RegFileFF = 0, + RegFileFPGA = 1, + RegFileLatch = 2 + } regfile_e; + + typedef enum integer { + RV32MNone = 0, + RV32MSlow = 1, + RV32MFast = 2, + RV32MSingleCycle = 3 + } rv32m_e; + + typedef enum integer { + RV32BNone = 0, + RV32BBalanced = 1, + RV32BFull = 2 + } rv32b_e; + + ///////////// + // Opcodes // + ///////////// + + typedef enum logic [6:0] { + OPCODE_LOAD = 7'h03, + OPCODE_MISC_MEM = 7'h0f, + OPCODE_OP_IMM = 7'h13, + OPCODE_AUIPC = 7'h17, + OPCODE_STORE = 7'h23, + OPCODE_OP = 7'h33, + OPCODE_LUI = 7'h37, + OPCODE_BRANCH = 7'h63, + OPCODE_JALR = 7'h67, + OPCODE_JAL = 7'h6f, + OPCODE_SYSTEM = 7'h73 + } opcode_e; + + + //////////////////// + // ALU operations // + //////////////////// + + typedef enum logic [5:0] { + // Arithmetics + ALU_ADD, + ALU_SUB, + + // Logics + ALU_XOR, + ALU_OR, + ALU_AND, + // RV32B + ALU_XNOR, + ALU_ORN, + ALU_ANDN, + + // Shifts + ALU_SRA, + ALU_SRL, + ALU_SLL, + // RV32B + ALU_SRO, + ALU_SLO, + ALU_ROR, + ALU_ROL, + ALU_GREV, + ALU_GORC, + ALU_SHFL, + ALU_UNSHFL, + + // Comparisons + ALU_LT, + ALU_LTU, + ALU_GE, + ALU_GEU, + ALU_EQ, + ALU_NE, + // RV32B + ALU_MIN, + ALU_MINU, + ALU_MAX, + ALU_MAXU, + + // Pack + // RV32B + ALU_PACK, + ALU_PACKU, + ALU_PACKH, + + // Sign-Extend + // RV32B + ALU_SEXTB, + ALU_SEXTH, + + // Bitcounting + // RV32B + ALU_CLZ, + ALU_CTZ, + ALU_PCNT, + + // Set lower than + ALU_SLT, + ALU_SLTU, + + // Ternary Bitmanip Operations + // RV32B + ALU_CMOV, + ALU_CMIX, + ALU_FSL, + ALU_FSR, + + // Single-Bit Operations + // RV32B + ALU_SBSET, + ALU_SBCLR, + ALU_SBINV, + ALU_SBEXT, + + // Bit Extract / Deposit + // RV32B + ALU_BEXT, + ALU_BDEP, + + // Bit Field Place + // RV32B + ALU_BFP, + + // Carry-less Multiply + // RV32B + ALU_CLMUL, + ALU_CLMULR, + ALU_CLMULH, + + // Cyclic Redundancy Check + ALU_CRC32_B, + ALU_CRC32C_B, + ALU_CRC32_H, + ALU_CRC32C_H, + ALU_CRC32_W, + ALU_CRC32C_W + } alu_op_e; + + typedef enum logic [1:0] { + // Multiplier/divider + MD_OP_MULL, + MD_OP_MULH, + MD_OP_DIV, + MD_OP_REM + } md_op_e; + + + ////////////////////////////////// + // Control and status registers // + ////////////////////////////////// + + // CSR operations + typedef enum logic [1:0] { + CSR_OP_READ, + CSR_OP_WRITE, + CSR_OP_SET, + CSR_OP_CLEAR + } csr_op_e; + + // Privileged mode + typedef enum logic[1:0] { + PRIV_LVL_M = 2'b11, + PRIV_LVL_H = 2'b10, + PRIV_LVL_S = 2'b01, + PRIV_LVL_U = 2'b00 + } priv_lvl_e; + + // Constants for the dcsr.xdebugver fields + typedef enum logic[3:0] { + XDEBUGVER_NO = 4'd0, // no external debug support + XDEBUGVER_STD = 4'd4, // external debug according to RISC-V debug spec + XDEBUGVER_NONSTD = 4'd15 // debug not conforming to RISC-V debug spec + } x_debug_ver_e; + + ////////////// + // WB stage // + ////////////// + + // Type of instruction present in writeback stage + typedef enum logic[1:0] { + WB_INSTR_LOAD, // Instruction is awaiting load data + WB_INSTR_STORE, // Instruction is awaiting store response + WB_INSTR_OTHER // Instruction doesn't fit into above categories + } wb_instr_type_e; + + ////////////// + // ID stage // + ////////////// + + // Operand a selection + typedef enum logic[1:0] { + OP_A_REG_A, + OP_A_FWD, + OP_A_CURRPC, + OP_A_IMM + } op_a_sel_e; + + // Immediate a selection + typedef enum logic { + IMM_A_Z, + IMM_A_ZERO + } imm_a_sel_e; + + // Operand b selection + typedef enum logic { + OP_B_REG_B, + OP_B_IMM + } op_b_sel_e; + + // Immediate b selection + typedef enum logic [2:0] { + IMM_B_I, + IMM_B_S, + IMM_B_B, + IMM_B_U, + IMM_B_J, + IMM_B_INCR_PC, + IMM_B_INCR_ADDR + } imm_b_sel_e; + + // Regfile write data selection + typedef enum logic { + RF_WD_EX, + RF_WD_CSR + } rf_wd_sel_e; + + ////////////// + // IF stage // + ////////////// + + // PC mux selection + typedef enum logic [2:0] { + PC_BOOT, + PC_JUMP, + PC_EXC, + PC_ERET, + PC_DRET, + PC_BP + } pc_sel_e; + + // Exception PC mux selection + typedef enum logic [1:0] { + EXC_PC_EXC, + EXC_PC_IRQ, + EXC_PC_DBD, + EXC_PC_DBG_EXC // Exception while in debug mode + } exc_pc_sel_e; + + // Interrupt requests + typedef struct packed { + logic irq_software; + logic irq_timer; + logic irq_external; + logic [14:0] irq_fast; // 15 fast interrupts, + // one interrupt is reserved for NMI (not visible through mip/mie) + } irqs_t; + + // Exception cause + typedef enum logic [5:0] { + EXC_CAUSE_IRQ_SOFTWARE_M = {1'b1, 5'd03}, + EXC_CAUSE_IRQ_TIMER_M = {1'b1, 5'd07}, + EXC_CAUSE_IRQ_EXTERNAL_M = {1'b1, 5'd11}, + // EXC_CAUSE_IRQ_FAST_0 = {1'b1, 5'd16}, + // EXC_CAUSE_IRQ_FAST_14 = {1'b1, 5'd30}, + EXC_CAUSE_IRQ_NM = {1'b1, 5'd31}, // == EXC_CAUSE_IRQ_FAST_15 + EXC_CAUSE_INSN_ADDR_MISA = {1'b0, 5'd00}, + EXC_CAUSE_INSTR_ACCESS_FAULT = {1'b0, 5'd01}, + EXC_CAUSE_ILLEGAL_INSN = {1'b0, 5'd02}, + EXC_CAUSE_BREAKPOINT = {1'b0, 5'd03}, + EXC_CAUSE_LOAD_ACCESS_FAULT = {1'b0, 5'd05}, + EXC_CAUSE_STORE_ACCESS_FAULT = {1'b0, 5'd07}, + EXC_CAUSE_ECALL_UMODE = {1'b0, 5'd08}, + EXC_CAUSE_ECALL_MMODE = {1'b0, 5'd11} + } exc_cause_e; + + // Debug cause + typedef enum logic [2:0] { + DBG_CAUSE_NONE = 3'h0, + DBG_CAUSE_EBREAK = 3'h1, + DBG_CAUSE_TRIGGER = 3'h2, + DBG_CAUSE_HALTREQ = 3'h3, + DBG_CAUSE_STEP = 3'h4 + } dbg_cause_e; + + // ICache constants + parameter int unsigned ADDR_W = 32; + parameter int unsigned BUS_SIZE = 32; + parameter int unsigned BUS_BYTES = BUS_SIZE/8; + parameter int unsigned BUS_W = $clog2(BUS_BYTES); + parameter int unsigned IC_SIZE_BYTES = 4096; + parameter int unsigned IC_NUM_WAYS = 2; + parameter int unsigned IC_LINE_SIZE = 64; + parameter int unsigned IC_LINE_BYTES = IC_LINE_SIZE/8; + parameter int unsigned IC_LINE_W = $clog2(IC_LINE_BYTES); + parameter int unsigned IC_NUM_LINES = IC_SIZE_BYTES / IC_NUM_WAYS / IC_LINE_BYTES; + parameter int unsigned IC_LINE_BEATS = IC_LINE_BYTES / BUS_BYTES; + parameter int unsigned IC_LINE_BEATS_W = $clog2(IC_LINE_BEATS); + parameter int unsigned IC_INDEX_W = $clog2(IC_NUM_LINES); + parameter int unsigned IC_INDEX_HI = IC_INDEX_W + IC_LINE_W - 1; + parameter int unsigned IC_TAG_SIZE = ADDR_W - IC_INDEX_W - IC_LINE_W + 1; // 1 valid bit + parameter int unsigned IC_OUTPUT_BEATS = (BUS_BYTES / 2); // number of halfwords + + // PMP constants + parameter int unsigned PMP_MAX_REGIONS = 16; + parameter int unsigned PMP_CFG_W = 8; + + // PMP acces type + parameter int unsigned PMP_I = 0; + parameter int unsigned PMP_D = 1; + + typedef enum logic [1:0] { + PMP_ACC_EXEC = 2'b00, + PMP_ACC_WRITE = 2'b01, + PMP_ACC_READ = 2'b10 + } pmp_req_e; + + // PMP cfg structures + typedef enum logic [1:0] { + PMP_MODE_OFF = 2'b00, + PMP_MODE_TOR = 2'b01, + PMP_MODE_NA4 = 2'b10, + PMP_MODE_NAPOT = 2'b11 + } pmp_cfg_mode_e; + + typedef struct packed { + logic lock; + pmp_cfg_mode_e mode; + logic exec; + logic write; + logic read; + } pmp_cfg_t; + + // Machine Security Configuration (ePMP) + typedef struct packed { + logic rlb; // Rule Locking Bypass + logic mmwp; // Machine Mode Whitelist Policy + logic mml; // Machine Mode Lockdown + } pmp_mseccfg_t; + + // CSRs + typedef enum logic[11:0] { + // Machine information + CSR_MHARTID = 12'hF14, + + // Machine trap setup + CSR_MSTATUS = 12'h300, + CSR_MISA = 12'h301, + CSR_MIE = 12'h304, + CSR_MTVEC = 12'h305, + CSR_MCOUNTEREN= 12'h306, + + // Machine trap handling + CSR_MSCRATCH = 12'h340, + CSR_MEPC = 12'h341, + CSR_MCAUSE = 12'h342, + CSR_MTVAL = 12'h343, + CSR_MIP = 12'h344, + + // Physical memory protection + CSR_PMPCFG0 = 12'h3A0, + CSR_PMPCFG1 = 12'h3A1, + CSR_PMPCFG2 = 12'h3A2, + CSR_PMPCFG3 = 12'h3A3, + CSR_PMPADDR0 = 12'h3B0, + CSR_PMPADDR1 = 12'h3B1, + CSR_PMPADDR2 = 12'h3B2, + CSR_PMPADDR3 = 12'h3B3, + CSR_PMPADDR4 = 12'h3B4, + CSR_PMPADDR5 = 12'h3B5, + CSR_PMPADDR6 = 12'h3B6, + CSR_PMPADDR7 = 12'h3B7, + CSR_PMPADDR8 = 12'h3B8, + CSR_PMPADDR9 = 12'h3B9, + CSR_PMPADDR10 = 12'h3BA, + CSR_PMPADDR11 = 12'h3BB, + CSR_PMPADDR12 = 12'h3BC, + CSR_PMPADDR13 = 12'h3BD, + CSR_PMPADDR14 = 12'h3BE, + CSR_PMPADDR15 = 12'h3BF, + + // ePMP control + CSR_MSECCFG = 12'h747, + CSR_MSECCFGH = 12'h757, + + // Debug trigger + CSR_TSELECT = 12'h7A0, + CSR_TDATA1 = 12'h7A1, + CSR_TDATA2 = 12'h7A2, + CSR_TDATA3 = 12'h7A3, + CSR_MCONTEXT = 12'h7A8, + CSR_SCONTEXT = 12'h7AA, + + // Debug/trace + CSR_DCSR = 12'h7b0, + CSR_DPC = 12'h7b1, + + // Debug + CSR_DSCRATCH0 = 12'h7b2, // optional + CSR_DSCRATCH1 = 12'h7b3, // optional + + // Machine Counter/Timers + CSR_MCOUNTINHIBIT = 12'h320, + CSR_MHPMEVENT3 = 12'h323, + CSR_MHPMEVENT4 = 12'h324, + CSR_MHPMEVENT5 = 12'h325, + CSR_MHPMEVENT6 = 12'h326, + CSR_MHPMEVENT7 = 12'h327, + CSR_MHPMEVENT8 = 12'h328, + CSR_MHPMEVENT9 = 12'h329, + CSR_MHPMEVENT10 = 12'h32A, + CSR_MHPMEVENT11 = 12'h32B, + CSR_MHPMEVENT12 = 12'h32C, + CSR_MHPMEVENT13 = 12'h32D, + CSR_MHPMEVENT14 = 12'h32E, + CSR_MHPMEVENT15 = 12'h32F, + CSR_MHPMEVENT16 = 12'h330, + CSR_MHPMEVENT17 = 12'h331, + CSR_MHPMEVENT18 = 12'h332, + CSR_MHPMEVENT19 = 12'h333, + CSR_MHPMEVENT20 = 12'h334, + CSR_MHPMEVENT21 = 12'h335, + CSR_MHPMEVENT22 = 12'h336, + CSR_MHPMEVENT23 = 12'h337, + CSR_MHPMEVENT24 = 12'h338, + CSR_MHPMEVENT25 = 12'h339, + CSR_MHPMEVENT26 = 12'h33A, + CSR_MHPMEVENT27 = 12'h33B, + CSR_MHPMEVENT28 = 12'h33C, + CSR_MHPMEVENT29 = 12'h33D, + CSR_MHPMEVENT30 = 12'h33E, + CSR_MHPMEVENT31 = 12'h33F, + CSR_MCYCLE = 12'hB00, + CSR_MINSTRET = 12'hB02, + CSR_MHPMCOUNTER3 = 12'hB03, + CSR_MHPMCOUNTER4 = 12'hB04, + CSR_MHPMCOUNTER5 = 12'hB05, + CSR_MHPMCOUNTER6 = 12'hB06, + CSR_MHPMCOUNTER7 = 12'hB07, + CSR_MHPMCOUNTER8 = 12'hB08, + CSR_MHPMCOUNTER9 = 12'hB09, + CSR_MHPMCOUNTER10 = 12'hB0A, + CSR_MHPMCOUNTER11 = 12'hB0B, + CSR_MHPMCOUNTER12 = 12'hB0C, + CSR_MHPMCOUNTER13 = 12'hB0D, + CSR_MHPMCOUNTER14 = 12'hB0E, + CSR_MHPMCOUNTER15 = 12'hB0F, + CSR_MHPMCOUNTER16 = 12'hB10, + CSR_MHPMCOUNTER17 = 12'hB11, + CSR_MHPMCOUNTER18 = 12'hB12, + CSR_MHPMCOUNTER19 = 12'hB13, + CSR_MHPMCOUNTER20 = 12'hB14, + CSR_MHPMCOUNTER21 = 12'hB15, + CSR_MHPMCOUNTER22 = 12'hB16, + CSR_MHPMCOUNTER23 = 12'hB17, + CSR_MHPMCOUNTER24 = 12'hB18, + CSR_MHPMCOUNTER25 = 12'hB19, + CSR_MHPMCOUNTER26 = 12'hB1A, + CSR_MHPMCOUNTER27 = 12'hB1B, + CSR_MHPMCOUNTER28 = 12'hB1C, + CSR_MHPMCOUNTER29 = 12'hB1D, + CSR_MHPMCOUNTER30 = 12'hB1E, + CSR_MHPMCOUNTER31 = 12'hB1F, + CSR_MCYCLEH = 12'hB80, + CSR_MINSTRETH = 12'hB82, + CSR_MHPMCOUNTER3H = 12'hB83, + CSR_MHPMCOUNTER4H = 12'hB84, + CSR_MHPMCOUNTER5H = 12'hB85, + CSR_MHPMCOUNTER6H = 12'hB86, + CSR_MHPMCOUNTER7H = 12'hB87, + CSR_MHPMCOUNTER8H = 12'hB88, + CSR_MHPMCOUNTER9H = 12'hB89, + CSR_MHPMCOUNTER10H = 12'hB8A, + CSR_MHPMCOUNTER11H = 12'hB8B, + CSR_MHPMCOUNTER12H = 12'hB8C, + CSR_MHPMCOUNTER13H = 12'hB8D, + CSR_MHPMCOUNTER14H = 12'hB8E, + CSR_MHPMCOUNTER15H = 12'hB8F, + CSR_MHPMCOUNTER16H = 12'hB90, + CSR_MHPMCOUNTER17H = 12'hB91, + CSR_MHPMCOUNTER18H = 12'hB92, + CSR_MHPMCOUNTER19H = 12'hB93, + CSR_MHPMCOUNTER20H = 12'hB94, + CSR_MHPMCOUNTER21H = 12'hB95, + CSR_MHPMCOUNTER22H = 12'hB96, + CSR_MHPMCOUNTER23H = 12'hB97, + CSR_MHPMCOUNTER24H = 12'hB98, + CSR_MHPMCOUNTER25H = 12'hB99, + CSR_MHPMCOUNTER26H = 12'hB9A, + CSR_MHPMCOUNTER27H = 12'hB9B, + CSR_MHPMCOUNTER28H = 12'hB9C, + CSR_MHPMCOUNTER29H = 12'hB9D, + CSR_MHPMCOUNTER30H = 12'hB9E, + CSR_MHPMCOUNTER31H = 12'hB9F, + CSR_CPUCTRL = 12'h7C0, + CSR_SECURESEED = 12'h7C1 + } csr_num_e; + + // CSR pmp-related offsets + parameter logic [11:0] CSR_OFF_PMP_CFG = 12'h3A0; // pmp_cfg @ 12'h3a0 - 12'h3a3 + parameter logic [11:0] CSR_OFF_PMP_ADDR = 12'h3B0; // pmp_addr @ 12'h3b0 - 12'h3bf + + // CSR status bits + parameter int unsigned CSR_MSTATUS_MIE_BIT = 3; + parameter int unsigned CSR_MSTATUS_MPIE_BIT = 7; + parameter int unsigned CSR_MSTATUS_MPP_BIT_LOW = 11; + parameter int unsigned CSR_MSTATUS_MPP_BIT_HIGH = 12; + parameter int unsigned CSR_MSTATUS_MPRV_BIT = 17; + parameter int unsigned CSR_MSTATUS_TW_BIT = 21; + + // CSR machine ISA + parameter logic [1:0] CSR_MISA_MXL = 2'd1; // M-XLEN: XLEN in M-Mode for RV32 + + // CSR interrupt pending/enable bits + parameter int unsigned CSR_MSIX_BIT = 3; + parameter int unsigned CSR_MTIX_BIT = 7; + parameter int unsigned CSR_MEIX_BIT = 11; + parameter int unsigned CSR_MFIX_BIT_LOW = 16; + parameter int unsigned CSR_MFIX_BIT_HIGH = 30; + + // CSR Machine Security Configuration bits + parameter int unsigned CSR_MSECCFG_MML_BIT = 0; + parameter int unsigned CSR_MSECCFG_MMWP_BIT = 1; + parameter int unsigned CSR_MSECCFG_RLB_BIT = 2; + + // These LFSR parameters have been generated with + // $ opentitan/util/design/gen-lfsr-seed.py --width 32 --seed 2480124384 --prefix "" + parameter int LfsrWidth = 32; + typedef logic [LfsrWidth-1:0] lfsr_seed_t; + typedef logic [LfsrWidth-1:0][$clog2(LfsrWidth)-1:0] lfsr_perm_t; + parameter lfsr_seed_t RndCnstLfsrSeedDefault = 32'hac533bf4; + parameter lfsr_perm_t RndCnstLfsrPermDefault = { + 160'h1e35ecba467fd1b12e958152c04fa43878a8daed + }; endpackage diff --git a/rtl/ibex_tracer_pkg.sv b/rtl/ibex_tracer_pkg.sv index c7947868..b5972fac 100644 --- a/rtl/ibex_tracer_pkg.sv +++ b/rtl/ibex_tracer_pkg.sv @@ -4,310 +4,316 @@ // SPDX-License-Identifier: Apache-2.0 package ibex_tracer_pkg; -import ibex_pkg::*; + import ibex_pkg::*; -parameter logic [1:0] OPCODE_C0 = 2'b00; -parameter logic [1:0] OPCODE_C1 = 2'b01; -parameter logic [1:0] OPCODE_C2 = 2'b10; + parameter logic [1:0] OPCODE_C0 = 2'b00; + parameter logic [1:0] OPCODE_C1 = 2'b01; + parameter logic [1:0] OPCODE_C2 = 2'b10; -// instruction masks (for tracer) -parameter logic [31:0] INSN_LUI = { 25'h?, {OPCODE_LUI } }; -parameter logic [31:0] INSN_AUIPC = { 25'h?, {OPCODE_AUIPC} }; -parameter logic [31:0] INSN_JAL = { 25'h?, {OPCODE_JAL } }; -parameter logic [31:0] INSN_JALR = { 17'h?, 3'b000, 5'h?, {OPCODE_JALR } }; + // instruction masks (for tracer) + parameter logic [31:0] INSN_LUI = { 25'h?, {OPCODE_LUI } }; + parameter logic [31:0] INSN_AUIPC = { 25'h?, {OPCODE_AUIPC} }; + parameter logic [31:0] INSN_JAL = { 25'h?, {OPCODE_JAL } }; + parameter logic [31:0] INSN_JALR = { 17'h?, 3'b000, 5'h?, {OPCODE_JALR } }; -// BRANCH -parameter logic [31:0] INSN_BEQ = { 17'h?, 3'b000, 5'h?, {OPCODE_BRANCH} }; -parameter logic [31:0] INSN_BNE = { 17'h?, 3'b001, 5'h?, {OPCODE_BRANCH} }; -parameter logic [31:0] INSN_BLT = { 17'h?, 3'b100, 5'h?, {OPCODE_BRANCH} }; -parameter logic [31:0] INSN_BGE = { 17'h?, 3'b101, 5'h?, {OPCODE_BRANCH} }; -parameter logic [31:0] INSN_BLTU = { 17'h?, 3'b110, 5'h?, {OPCODE_BRANCH} }; -parameter logic [31:0] INSN_BGEU = { 17'h?, 3'b111, 5'h?, {OPCODE_BRANCH} }; + // BRANCH + parameter logic [31:0] INSN_BEQ = { 17'h?, 3'b000, 5'h?, {OPCODE_BRANCH} }; + parameter logic [31:0] INSN_BNE = { 17'h?, 3'b001, 5'h?, {OPCODE_BRANCH} }; + parameter logic [31:0] INSN_BLT = { 17'h?, 3'b100, 5'h?, {OPCODE_BRANCH} }; + parameter logic [31:0] INSN_BGE = { 17'h?, 3'b101, 5'h?, {OPCODE_BRANCH} }; + parameter logic [31:0] INSN_BLTU = { 17'h?, 3'b110, 5'h?, {OPCODE_BRANCH} }; + parameter logic [31:0] INSN_BGEU = { 17'h?, 3'b111, 5'h?, {OPCODE_BRANCH} }; -// OPIMM -parameter logic [31:0] INSN_ADDI = { 17'h?, 3'b000, 5'h?, {OPCODE_OP_IMM} }; -parameter logic [31:0] INSN_SLTI = { 17'h?, 3'b010, 5'h?, {OPCODE_OP_IMM} }; -parameter logic [31:0] INSN_SLTIU = { 17'h?, 3'b011, 5'h?, {OPCODE_OP_IMM} }; -parameter logic [31:0] INSN_XORI = { 17'h?, 3'b100, 5'h?, {OPCODE_OP_IMM} }; -parameter logic [31:0] INSN_ORI = { 17'h?, 3'b110, 5'h?, {OPCODE_OP_IMM} }; -parameter logic [31:0] INSN_ANDI = { 17'h?, 3'b111, 5'h?, {OPCODE_OP_IMM} }; -parameter logic [31:0] INSN_SLLI = { 7'b0000000, 10'h?, 3'b001, 5'h?, {OPCODE_OP_IMM} }; -parameter logic [31:0] INSN_SRLI = { 7'b0000000, 10'h?, 3'b101, 5'h?, {OPCODE_OP_IMM} }; -parameter logic [31:0] INSN_SRAI = { 7'b0100000, 10'h?, 3'b101, 5'h?, {OPCODE_OP_IMM} }; + // OPIMM + parameter logic [31:0] INSN_ADDI = { 17'h?, 3'b000, 5'h?, {OPCODE_OP_IMM} }; + parameter logic [31:0] INSN_SLTI = { 17'h?, 3'b010, 5'h?, {OPCODE_OP_IMM} }; + parameter logic [31:0] INSN_SLTIU = { 17'h?, 3'b011, 5'h?, {OPCODE_OP_IMM} }; + parameter logic [31:0] INSN_XORI = { 17'h?, 3'b100, 5'h?, {OPCODE_OP_IMM} }; + parameter logic [31:0] INSN_ORI = { 17'h?, 3'b110, 5'h?, {OPCODE_OP_IMM} }; + parameter logic [31:0] INSN_ANDI = { 17'h?, 3'b111, 5'h?, {OPCODE_OP_IMM} }; + parameter logic [31:0] INSN_SLLI = { 7'b0000000, 10'h?, 3'b001, 5'h?, {OPCODE_OP_IMM} }; + parameter logic [31:0] INSN_SRLI = { 7'b0000000, 10'h?, 3'b101, 5'h?, {OPCODE_OP_IMM} }; + parameter logic [31:0] INSN_SRAI = { 7'b0100000, 10'h?, 3'b101, 5'h?, {OPCODE_OP_IMM} }; -// OP -parameter logic [31:0] INSN_ADD = { 7'b0000000, 10'h?, 3'b000, 5'h?, {OPCODE_OP} }; -parameter logic [31:0] INSN_SUB = { 7'b0100000, 10'h?, 3'b000, 5'h?, {OPCODE_OP} }; -parameter logic [31:0] INSN_SLL = { 7'b0000000, 10'h?, 3'b001, 5'h?, {OPCODE_OP} }; -parameter logic [31:0] INSN_SLT = { 7'b0000000, 10'h?, 3'b010, 5'h?, {OPCODE_OP} }; -parameter logic [31:0] INSN_SLTU = { 7'b0000000, 10'h?, 3'b011, 5'h?, {OPCODE_OP} }; -parameter logic [31:0] INSN_XOR = { 7'b0000000, 10'h?, 3'b100, 5'h?, {OPCODE_OP} }; -parameter logic [31:0] INSN_SRL = { 7'b0000000, 10'h?, 3'b101, 5'h?, {OPCODE_OP} }; -parameter logic [31:0] INSN_SRA = { 7'b0100000, 10'h?, 3'b101, 5'h?, {OPCODE_OP} }; -parameter logic [31:0] INSN_OR = { 7'b0000000, 10'h?, 3'b110, 5'h?, {OPCODE_OP} }; -parameter logic [31:0] INSN_AND = { 7'b0000000, 10'h?, 3'b111, 5'h?, {OPCODE_OP} }; + // OP + parameter logic [31:0] INSN_ADD = { 7'b0000000, 10'h?, 3'b000, 5'h?, {OPCODE_OP} }; + parameter logic [31:0] INSN_SUB = { 7'b0100000, 10'h?, 3'b000, 5'h?, {OPCODE_OP} }; + parameter logic [31:0] INSN_SLL = { 7'b0000000, 10'h?, 3'b001, 5'h?, {OPCODE_OP} }; + parameter logic [31:0] INSN_SLT = { 7'b0000000, 10'h?, 3'b010, 5'h?, {OPCODE_OP} }; + parameter logic [31:0] INSN_SLTU = { 7'b0000000, 10'h?, 3'b011, 5'h?, {OPCODE_OP} }; + parameter logic [31:0] INSN_XOR = { 7'b0000000, 10'h?, 3'b100, 5'h?, {OPCODE_OP} }; + parameter logic [31:0] INSN_SRL = { 7'b0000000, 10'h?, 3'b101, 5'h?, {OPCODE_OP} }; + parameter logic [31:0] INSN_SRA = { 7'b0100000, 10'h?, 3'b101, 5'h?, {OPCODE_OP} }; + parameter logic [31:0] INSN_OR = { 7'b0000000, 10'h?, 3'b110, 5'h?, {OPCODE_OP} }; + parameter logic [31:0] INSN_AND = { 7'b0000000, 10'h?, 3'b111, 5'h?, {OPCODE_OP} }; -// SYSTEM -parameter logic [31:0] INSN_CSRRW = { 17'h?, 3'b001, 5'h?, {OPCODE_SYSTEM} }; -parameter logic [31:0] INSN_CSRRS = { 17'h?, 3'b010, 5'h?, {OPCODE_SYSTEM} }; -parameter logic [31:0] INSN_CSRRC = { 17'h?, 3'b011, 5'h?, {OPCODE_SYSTEM} }; -parameter logic [31:0] INSN_CSRRWI = { 17'h?, 3'b101, 5'h?, {OPCODE_SYSTEM} }; -parameter logic [31:0] INSN_CSRRSI = { 17'h?, 3'b110, 5'h?, {OPCODE_SYSTEM} }; -parameter logic [31:0] INSN_CSRRCI = { 17'h?, 3'b111, 5'h?, {OPCODE_SYSTEM} }; -parameter logic [31:0] INSN_ECALL = { 12'b000000000000, 13'b0, {OPCODE_SYSTEM} }; -parameter logic [31:0] INSN_EBREAK = { 12'b000000000001, 13'b0, {OPCODE_SYSTEM} }; -parameter logic [31:0] INSN_MRET = { 12'b001100000010, 13'b0, {OPCODE_SYSTEM} }; -parameter logic [31:0] INSN_DRET = { 12'b011110110010, 13'b0, {OPCODE_SYSTEM} }; -parameter logic [31:0] INSN_WFI = { 12'b000100000101, 13'b0, {OPCODE_SYSTEM} }; + // SYSTEM + parameter logic [31:0] INSN_CSRRW = { 17'h?, 3'b001, 5'h?, {OPCODE_SYSTEM} }; + parameter logic [31:0] INSN_CSRRS = { 17'h?, 3'b010, 5'h?, {OPCODE_SYSTEM} }; + parameter logic [31:0] INSN_CSRRC = { 17'h?, 3'b011, 5'h?, {OPCODE_SYSTEM} }; + parameter logic [31:0] INSN_CSRRWI = { 17'h?, 3'b101, 5'h?, {OPCODE_SYSTEM} }; + parameter logic [31:0] INSN_CSRRSI = { 17'h?, 3'b110, 5'h?, {OPCODE_SYSTEM} }; + parameter logic [31:0] INSN_CSRRCI = { 17'h?, 3'b111, 5'h?, {OPCODE_SYSTEM} }; + parameter logic [31:0] INSN_ECALL = { 12'b000000000000, 13'b0, {OPCODE_SYSTEM} }; + parameter logic [31:0] INSN_EBREAK = { 12'b000000000001, 13'b0, {OPCODE_SYSTEM} }; + parameter logic [31:0] INSN_MRET = { 12'b001100000010, 13'b0, {OPCODE_SYSTEM} }; + parameter logic [31:0] INSN_DRET = { 12'b011110110010, 13'b0, {OPCODE_SYSTEM} }; + parameter logic [31:0] INSN_WFI = { 12'b000100000101, 13'b0, {OPCODE_SYSTEM} }; -// RV32M -parameter logic [31:0] INSN_DIV = { 7'b0000001, 10'h?, 3'b100, 5'h?, {OPCODE_OP} }; -parameter logic [31:0] INSN_DIVU = { 7'b0000001, 10'h?, 3'b101, 5'h?, {OPCODE_OP} }; -parameter logic [31:0] INSN_REM = { 7'b0000001, 10'h?, 3'b110, 5'h?, {OPCODE_OP} }; -parameter logic [31:0] INSN_REMU = { 7'b0000001, 10'h?, 3'b111, 5'h?, {OPCODE_OP} }; -parameter logic [31:0] INSN_PMUL = { 7'b0000001, 10'h?, 3'b000, 5'h?, {OPCODE_OP} }; -parameter logic [31:0] INSN_PMUH = { 7'b0000001, 10'h?, 3'b001, 5'h?, {OPCODE_OP} }; -parameter logic [31:0] INSN_PMULHSU = { 7'b0000001, 10'h?, 3'b010, 5'h?, {OPCODE_OP} }; -parameter logic [31:0] INSN_PMULHU = { 7'b0000001, 10'h?, 3'b011, 5'h?, {OPCODE_OP} }; + // RV32M + parameter logic [31:0] INSN_DIV = { 7'b0000001, 10'h?, 3'b100, 5'h?, {OPCODE_OP} }; + parameter logic [31:0] INSN_DIVU = { 7'b0000001, 10'h?, 3'b101, 5'h?, {OPCODE_OP} }; + parameter logic [31:0] INSN_REM = { 7'b0000001, 10'h?, 3'b110, 5'h?, {OPCODE_OP} }; + parameter logic [31:0] INSN_REMU = { 7'b0000001, 10'h?, 3'b111, 5'h?, {OPCODE_OP} }; + parameter logic [31:0] INSN_PMUL = { 7'b0000001, 10'h?, 3'b000, 5'h?, {OPCODE_OP} }; + parameter logic [31:0] INSN_PMUH = { 7'b0000001, 10'h?, 3'b001, 5'h?, {OPCODE_OP} }; + parameter logic [31:0] INSN_PMULHSU = { 7'b0000001, 10'h?, 3'b010, 5'h?, {OPCODE_OP} }; + parameter logic [31:0] INSN_PMULHU = { 7'b0000001, 10'h?, 3'b011, 5'h?, {OPCODE_OP} }; -// RV32B -// ZBB -parameter logic [31:0] INSN_SLOI = { 5'b00100 , 12'h?, 3'b001, 5'h?, {OPCODE_OP_IMM} }; -// Only log2(XLEN) bits of the immediate are used. For RV32, this means only the bits in -// instr[24:20] are effectively used. Whenever instr[26] is set, sroi/rori is instead decoded as -// fsri. -parameter logic [31:0] INSN_SROI = { 5'b00100 , 1'b0, 11'h?, 3'b101, 5'h?, {OPCODE_OP_IMM} }; -parameter logic [31:0] INSN_RORI = { 5'b01100 , 1'b0, 11'h?, 3'b101, 5'h?, {OPCODE_OP_IMM} }; -parameter logic [31:0] INSN_CLZ = { 12'b011000000000, 5'h?, 3'b001, 5'h?, {OPCODE_OP_IMM} }; -parameter logic [31:0] INSN_CTZ = { 12'b011000000001, 5'h?, 3'b001, 5'h?, {OPCODE_OP_IMM} }; -parameter logic [31:0] INSN_PCNT = { 12'b011000000010, 5'h?, 3'b001, 5'h?, {OPCODE_OP_IMM} }; -parameter logic [31:0] INSN_SEXTB = { 12'b011000000100, 5'h?, 3'b001, 5'h?, {OPCODE_OP_IMM} }; -parameter logic [31:0] INSN_SEXTH = { 12'b011000000101, 5'h?, 3'b001, 5'h?, {OPCODE_OP_IMM} }; -// The ZEXT.B and ZEXT.H pseudo-instructions are currently not emitted by the tracer due to a lack -// of support in the LLVM and GCC toolchains. Enabling this functionality when the time is right is -// tracked in https://github.com/lowRISC/ibex/issues/1228 -// sext -- pseudoinstruction: andi rd, rs 255 -// parameter logic [31:0] INSN_ZEXTB = { 4'b0000, 8'b11111111, 5'h?, 3'b111, 5'h?, {OPCODE_OP_IMM} }; -// sext -- pseudoinstruction: pack rd, rs zero -// parameter logic [31:0] INSN_ZEXTH = { 7'b0000100, 5'b00000, 5'h?, 3'b100, 5'h?, {OPCODE_OP} }; + // RV32B + // ZBB + parameter logic [31:0] INSN_SLOI = { 5'b00100 , 12'h?, 3'b001, 5'h?, {OPCODE_OP_IMM} }; + // Only log2(XLEN) bits of the immediate are used. For RV32, this means only the bits in + // instr[24:20] are effectively used. Whenever instr[26] is set, sroi/rori is instead decoded as + // fsri. + parameter logic [31:0] INSN_SROI = { 5'b00100 , 1'b0, 11'h?, 3'b101, 5'h?, {OPCODE_OP_IMM} }; + parameter logic [31:0] INSN_RORI = { 5'b01100 , 1'b0, 11'h?, 3'b101, 5'h?, {OPCODE_OP_IMM} }; + parameter logic [31:0] INSN_CLZ = { 12'b011000000000, 5'h?, 3'b001, 5'h?, {OPCODE_OP_IMM} }; + parameter logic [31:0] INSN_CTZ = { 12'b011000000001, 5'h?, 3'b001, 5'h?, {OPCODE_OP_IMM} }; + parameter logic [31:0] INSN_PCNT = { 12'b011000000010, 5'h?, 3'b001, 5'h?, {OPCODE_OP_IMM} }; + parameter logic [31:0] INSN_SEXTB = { 12'b011000000100, 5'h?, 3'b001, 5'h?, {OPCODE_OP_IMM} }; + parameter logic [31:0] INSN_SEXTH = { 12'b011000000101, 5'h?, 3'b001, 5'h?, {OPCODE_OP_IMM} }; + // The ZEXT.B and ZEXT.H pseudo-instructions are currently not emitted by the tracer due to a lack + // of support in the LLVM and GCC toolchains. Enabling this functionality when the time is right is + // tracked in https://github.com/lowRISC/ibex/issues/1228 + // sext -- pseudoinstruction: andi rd, rs 255 + // parameter logic [31:0] INSN_ZEXTB = { 4'b0000, 8'b11111111, 5'h?, 3'b111, 5'h?, {OPCODE_OP_IMM} }; + // sext -- pseudoinstruction: pack rd, rs zero + // parameter logic [31:0] INSN_ZEXTH = { 7'b0000100, 5'b00000, 5'h?, 3'b100, 5'h?, {OPCODE_OP} }; -parameter logic [31:0] INSN_SLO = { 7'b0010000, 10'h?, 3'b001, 5'h?, {OPCODE_OP} }; -parameter logic [31:0] INSN_SRO = { 7'b0010000, 10'h?, 3'b101, 5'h?, {OPCODE_OP} }; -parameter logic [31:0] INSN_ROL = { 7'b0110000, 10'h?, 3'b001, 5'h?, {OPCODE_OP} }; -parameter logic [31:0] INSN_ROR = { 7'b0110000, 10'h?, 3'b101, 5'h?, {OPCODE_OP} }; -parameter logic [31:0] INSN_MIN = { 7'b0000101, 10'h?, 3'b100, 5'h?, {OPCODE_OP} }; -parameter logic [31:0] INSN_MAX = { 7'b0000101, 10'h?, 3'b101, 5'h?, {OPCODE_OP} }; -parameter logic [31:0] INSN_MINU = { 7'b0000101, 10'h?, 3'b110, 5'h?, {OPCODE_OP} }; -parameter logic [31:0] INSN_MAXU = { 7'b0000101, 10'h?, 3'b111, 5'h?, {OPCODE_OP} }; -parameter logic [31:0] INSN_XNOR = { 7'b0100000, 10'h?, 3'b100, 5'h?, {OPCODE_OP} }; -parameter logic [31:0] INSN_ORN = { 7'b0100000, 10'h?, 3'b110, 5'h?, {OPCODE_OP} }; -parameter logic [31:0] INSN_ANDN = { 7'b0100000, 10'h?, 3'b111, 5'h?, {OPCODE_OP} }; -parameter logic [31:0] INSN_PACK = { 7'b0000100, 10'h?, 3'b100, 5'h?, {OPCODE_OP} }; -parameter logic [31:0] INSN_PACKU = { 7'b0100100, 10'h?, 3'b100, 5'h?, {OPCODE_OP} }; -parameter logic [31:0] INSN_PACKH = { 7'b0000100, 10'h?, 3'b111, 5'h?, {OPCODE_OP} }; + parameter logic [31:0] INSN_SLO = { 7'b0010000, 10'h?, 3'b001, 5'h?, {OPCODE_OP} }; + parameter logic [31:0] INSN_SRO = { 7'b0010000, 10'h?, 3'b101, 5'h?, {OPCODE_OP} }; + parameter logic [31:0] INSN_ROL = { 7'b0110000, 10'h?, 3'b001, 5'h?, {OPCODE_OP} }; + parameter logic [31:0] INSN_ROR = { 7'b0110000, 10'h?, 3'b101, 5'h?, {OPCODE_OP} }; + parameter logic [31:0] INSN_MIN = { 7'b0000101, 10'h?, 3'b100, 5'h?, {OPCODE_OP} }; + parameter logic [31:0] INSN_MAX = { 7'b0000101, 10'h?, 3'b101, 5'h?, {OPCODE_OP} }; + parameter logic [31:0] INSN_MINU = { 7'b0000101, 10'h?, 3'b110, 5'h?, {OPCODE_OP} }; + parameter logic [31:0] INSN_MAXU = { 7'b0000101, 10'h?, 3'b111, 5'h?, {OPCODE_OP} }; + parameter logic [31:0] INSN_XNOR = { 7'b0100000, 10'h?, 3'b100, 5'h?, {OPCODE_OP} }; + parameter logic [31:0] INSN_ORN = { 7'b0100000, 10'h?, 3'b110, 5'h?, {OPCODE_OP} }; + parameter logic [31:0] INSN_ANDN = { 7'b0100000, 10'h?, 3'b111, 5'h?, {OPCODE_OP} }; + parameter logic [31:0] INSN_PACK = { 7'b0000100, 10'h?, 3'b100, 5'h?, {OPCODE_OP} }; + parameter logic [31:0] INSN_PACKU = { 7'b0100100, 10'h?, 3'b100, 5'h?, {OPCODE_OP} }; + parameter logic [31:0] INSN_PACKH = { 7'b0000100, 10'h?, 3'b111, 5'h?, {OPCODE_OP} }; -// ZBS -parameter logic [31:0] INSN_SBCLRI = { 5'b01001, 12'h?, 3'b001, 5'h?, {OPCODE_OP_IMM} }; -parameter logic [31:0] INSN_SBSETI = { 5'b00101, 12'h?, 3'b001, 5'h?, {OPCODE_OP_IMM} }; -parameter logic [31:0] INSN_SBINVI = { 5'b01101, 12'h?, 3'b001, 5'h?, {OPCODE_OP_IMM} }; -// Only log2(XLEN) bits of the immediate are used. For RV32, this means only the bits in -// instr[24:20] are effectively used. Whenever instr[26] is set, sbexti is instead decoded as fsri. -parameter logic [31:0] INSN_SBEXTI = { 5'b01001, 1'b0, 11'h?, 3'b101, 5'h?, {OPCODE_OP_IMM} }; + // ZBS + parameter logic [31:0] INSN_SBCLRI = { 5'b01001, 12'h?, 3'b001, 5'h?, {OPCODE_OP_IMM} }; + parameter logic [31:0] INSN_SBSETI = { 5'b00101, 12'h?, 3'b001, 5'h?, {OPCODE_OP_IMM} }; + parameter logic [31:0] INSN_SBINVI = { 5'b01101, 12'h?, 3'b001, 5'h?, {OPCODE_OP_IMM} }; + // Only log2(XLEN) bits of the immediate are used. For RV32, this means only the bits in + // instr[24:20] are effectively used. Whenever instr[26] is set, sbexti is instead decoded as fsri. + parameter logic [31:0] INSN_SBEXTI = { 5'b01001, 1'b0, 11'h?, 3'b101, 5'h?, {OPCODE_OP_IMM} }; -parameter logic [31:0] INSN_SBCLR = { 7'b0100100, 10'h?, 3'b001, 5'h?, {OPCODE_OP} }; -parameter logic [31:0] INSN_SBSET = { 7'b0010100, 10'h?, 3'b001, 5'h?, {OPCODE_OP} }; -parameter logic [31:0] INSN_SBINV = { 7'b0110100, 10'h?, 3'b001, 5'h?, {OPCODE_OP} }; -parameter logic [31:0] INSN_SBEXT = { 7'b0100100, 10'h?, 3'b101, 5'h?, {OPCODE_OP} }; + parameter logic [31:0] INSN_SBCLR = { 7'b0100100, 10'h?, 3'b001, 5'h?, {OPCODE_OP} }; + parameter logic [31:0] INSN_SBSET = { 7'b0010100, 10'h?, 3'b001, 5'h?, {OPCODE_OP} }; + parameter logic [31:0] INSN_SBINV = { 7'b0110100, 10'h?, 3'b001, 5'h?, {OPCODE_OP} }; + parameter logic [31:0] INSN_SBEXT = { 7'b0100100, 10'h?, 3'b101, 5'h?, {OPCODE_OP} }; -// ZBP -// grevi -// Only log2(XLEN) bits of the immediate are used. For RV32, this means only the bits in -// instr[24:20] are effectively used. Whenever instr[26] is set, grevi is instead decoded as fsri. -parameter logic [31:0] INSN_GREVI = { 5'b01101, 1'b0, 11'h?, 3'b101, 5'h?, {OPCODE_OP_IMM} }; -// grevi -- pseudo-instructions -parameter logic [31:0] INSN_REV_P = - { 5'b01101, 1'b0, 1'b?, 5'b00001, 5'h?, 3'b101, 5'h?, {OPCODE_OP_IMM} }; -parameter logic [31:0] INSN_REV2_N = - { 5'b01101, 1'b0, 1'b?, 5'b00010, 5'h?, 3'b101, 5'h?, {OPCODE_OP_IMM} }; -parameter logic [31:0] INSN_REV_N = - { 5'b01101, 1'b0, 1'b?, 5'b00011, 5'h?, 3'b101, 5'h?, {OPCODE_OP_IMM} }; -parameter logic [31:0] INSN_REV4_B = - { 5'b01101, 1'b0, 1'b?, 5'b00100, 5'h?, 3'b101, 5'h?, {OPCODE_OP_IMM} }; -parameter logic [31:0] INSN_REV2_B = - { 5'b01101, 1'b0, 1'b?, 5'b00110, 5'h?, 3'b101, 5'h?, {OPCODE_OP_IMM} }; -parameter logic [31:0] INSN_REV_B = - { 5'b01101, 1'b0, 1'b?, 5'b00111, 5'h?, 3'b101, 5'h?, {OPCODE_OP_IMM} }; -parameter logic [31:0] INSN_REV8_H = - { 5'b01101, 1'b0, 1'b?, 5'b01000, 5'h?, 3'b101, 5'h?, {OPCODE_OP_IMM} }; -parameter logic [31:0] INSN_REV4_H = - { 5'b01101, 1'b0, 1'b?, 5'b01100, 5'h?, 3'b101, 5'h?, {OPCODE_OP_IMM} }; -parameter logic [31:0] INSN_REV2_H = - { 5'b01101, 1'b0, 1'b?, 5'b01110, 5'h?, 3'b101, 5'h?, {OPCODE_OP_IMM} }; -parameter logic [31:0] INSN_REV_H = - { 5'b01101, 1'b0, 1'b?, 5'b01111, 5'h?, 3'b101, 5'h?, {OPCODE_OP_IMM} }; -parameter logic [31:0] INSN_REV16 = - { 5'b01101, 1'b0, 1'b?, 5'b10000, 5'h?, 3'b101, 5'h?, {OPCODE_OP_IMM} }; -parameter logic [31:0] INSN_REV8 = - { 5'b01101, 1'b0, 1'b?, 5'b11000, 5'h?, 3'b101, 5'h?, {OPCODE_OP_IMM} }; -parameter logic [31:0] INSN_REV4 = - { 5'b01101, 1'b0, 1'b?, 5'b11100, 5'h?, 3'b101, 5'h?, {OPCODE_OP_IMM} }; -parameter logic [31:0] INSN_REV2 = - { 5'b01101, 1'b0, 1'b?, 5'b11110, 5'h?, 3'b101, 5'h?, {OPCODE_OP_IMM} }; -parameter logic [31:0] INSN_REV = - { 5'b01101, 1'b0, 1'b?, 5'b11111, 5'h?, 3'b101, 5'h?, {OPCODE_OP_IMM} }; -// gorci -// Only log2(XLEN) bits of the immediate are used. For RV32, this means only the bits in -// instr[24:20] are effectively used. Whenever instr[26] is set, gorci is instead decoded as fsri. -parameter logic [31:0] INSN_GORCI = { 5'b00101, 1'b0, 11'h?, 3'b101, 5'h?, {OPCODE_OP_IMM} }; -// gorci -- pseudo-instructions -parameter logic [31:0] INSN_ORC_P = - { 5'b00101, 1'b0, 1'b?, 5'b00001, 5'h?, 3'b101, 5'h?, {OPCODE_OP_IMM} }; -parameter logic [31:0] INSN_ORC2_N = - { 5'b00101, 1'b0, 1'b?, 5'b00010, 5'h?, 3'b101, 5'h?, {OPCODE_OP_IMM} }; -parameter logic [31:0] INSN_ORC_N = - { 5'b00101, 1'b0, 1'b?, 5'b00011, 5'h?, 3'b101, 5'h?, {OPCODE_OP_IMM} }; -parameter logic [31:0] INSN_ORC4_B = - { 5'b00101, 1'b0, 1'b?, 5'b00100, 5'h?, 3'b101, 5'h?, {OPCODE_OP_IMM} }; -parameter logic [31:0] INSN_ORC2_B = - { 5'b00101, 1'b0, 1'b?, 5'b00110, 5'h?, 3'b101, 5'h?, {OPCODE_OP_IMM} }; -parameter logic [31:0] INSN_ORC_B = - { 5'b00101, 1'b0, 1'b?, 5'b00111, 5'h?, 3'b101, 5'h?, {OPCODE_OP_IMM} }; -parameter logic [31:0] INSN_ORC8_H = - { 5'b00101, 1'b0, 1'b?, 5'b01000, 5'h?, 3'b101, 5'h?, {OPCODE_OP_IMM} }; -parameter logic [31:0] INSN_ORC4_H = - { 5'b00101, 1'b0, 1'b?, 5'b01100, 5'h?, 3'b101, 5'h?, {OPCODE_OP_IMM} }; -parameter logic [31:0] INSN_ORC2_H = - { 5'b00101, 1'b0, 1'b?, 5'b01110, 5'h?, 3'b101, 5'h?, {OPCODE_OP_IMM} }; -parameter logic [31:0] INSN_ORC_H = - { 5'b00101, 1'b0, 1'b?, 5'b01111, 5'h?, 3'b101, 5'h?, {OPCODE_OP_IMM} }; -parameter logic [31:0] INSN_ORC16 = - { 5'b00101, 1'b0, 1'b?, 5'b10000, 5'h?, 3'b101, 5'h?, {OPCODE_OP_IMM} }; -parameter logic [31:0] INSN_ORC8 = - { 5'b00101, 1'b0, 1'b?, 5'b11000, 5'h?, 3'b101, 5'h?, {OPCODE_OP_IMM} }; -parameter logic [31:0] INSN_ORC4 = - { 5'b00101, 1'b0, 1'b?, 5'b11100, 5'h?, 3'b101, 5'h?, {OPCODE_OP_IMM} }; -parameter logic [31:0] INSN_ORC2 = - { 5'b00101, 1'b0, 1'b?, 5'b11110, 5'h?, 3'b101, 5'h?, {OPCODE_OP_IMM} }; -parameter logic [31:0] INSN_ORC = - { 5'b00101, 1'b0, 1'b?, 5'b11111, 5'h?, 3'b101, 5'h?, {OPCODE_OP_IMM} }; -// shfli -parameter logic [31:0] INSN_SHFLI = { 6'b000010, 11'h?, 3'b001, 5'h?, {OPCODE_OP_IMM} }; -// shfli -- pseudo-instructions -parameter logic [31:0] INSN_ZIP_N = - { 6'b000010, 2'h?, 4'b0001, 5'h?, 3'b001, 5'h?, {OPCODE_OP_IMM} }; -parameter logic [31:0] INSN_ZIP2_B = - { 6'b000010, 2'h?, 4'b0010, 5'h?, 3'b001, 5'h?, {OPCODE_OP_IMM} }; -parameter logic [31:0] INSN_ZIP_B = - { 6'b000010, 2'h?, 4'b0011, 5'h?, 3'b001, 5'h?, {OPCODE_OP_IMM} }; -parameter logic [31:0] INSN_ZIP4_H = - { 6'b000010, 2'h?, 4'b0100, 5'h?, 3'b001, 5'h?, {OPCODE_OP_IMM} }; -parameter logic [31:0] INSN_ZIP2_H = - { 6'b000010, 2'h?, 4'b0110, 5'h?, 3'b001, 5'h?, {OPCODE_OP_IMM} }; -parameter logic [31:0] INSN_ZIP_H = - { 6'b000010, 2'h?, 4'b0111, 5'h?, 3'b001, 5'h?, {OPCODE_OP_IMM} }; -parameter logic [31:0] INSN_ZIP8 = - { 6'b000010, 2'h?, 4'b1000, 5'h?, 3'b001, 5'h?, {OPCODE_OP_IMM} }; -parameter logic [31:0] INSN_ZIP4 = - { 6'b000010, 2'h?, 4'b1100, 5'h?, 3'b001, 5'h?, {OPCODE_OP_IMM} }; -parameter logic [31:0] INSN_ZIP2 = - { 6'b000010, 2'h?, 4'b1110, 5'h?, 3'b001, 5'h?, {OPCODE_OP_IMM} }; -parameter logic [31:0] INSN_ZIP = - { 6'b000010, 2'h?, 4'b1111, 5'h?, 3'b001, 5'h?, {OPCODE_OP_IMM} }; -// unshfli -parameter logic [31:0] INSN_UNSHFLI = { 6'b000010, 11'h?, 3'b101, 5'h?, {OPCODE_OP_IMM} }; -// unshfli -- pseudo-instructions -parameter logic [31:0] INSN_UNZIP_N = - { 6'b000010, 2'h?, 4'b0001, 5'h?, 3'b101, 5'h?, {OPCODE_OP_IMM} }; -parameter logic [31:0] INSN_UNZIP2_B = - { 6'b000010, 2'h?, 4'b0010, 5'h?, 3'b101, 5'h?, {OPCODE_OP_IMM} }; -parameter logic [31:0] INSN_UNZIP_B = - { 6'b000010, 2'h?, 4'b0011, 5'h?, 3'b101, 5'h?, {OPCODE_OP_IMM} }; -parameter logic [31:0] INSN_UNZIP4_H = - { 6'b000010, 2'h?, 4'b0100, 5'h?, 3'b101, 5'h?, {OPCODE_OP_IMM} }; -parameter logic [31:0] INSN_UNZIP2_H = - { 6'b000010, 2'h?, 4'b0110, 5'h?, 3'b101, 5'h?, {OPCODE_OP_IMM} }; -parameter logic [31:0] INSN_UNZIP_H = - { 6'b000010, 2'h?, 4'b0111, 5'h?, 3'b101, 5'h?, {OPCODE_OP_IMM} }; -parameter logic [31:0] INSN_UNZIP8 = - { 6'b000010, 2'h?, 4'b1000, 5'h?, 3'b101, 5'h?, {OPCODE_OP_IMM} }; -parameter logic [31:0] INSN_UNZIP4 = - { 6'b000010, 2'h?, 4'b1100, 5'h?, 3'b101, 5'h?, {OPCODE_OP_IMM} }; -parameter logic [31:0] INSN_UNZIP2 = - { 6'b000010, 2'h?, 4'b1110, 5'h?, 3'b101, 5'h?, {OPCODE_OP_IMM} }; -parameter logic [31:0] INSN_UNZIP = - { 6'b000010, 2'h?, 4'b1111, 5'h?, 3'b101, 5'h?, {OPCODE_OP_IMM} }; + // ZBP + // grevi + // Only log2(XLEN) bits of the immediate are used. For RV32, this means only the bits in + // instr[24:20] are effectively used. Whenever instr[26] is set, grevi is instead decoded as fsri. + parameter logic [31:0] INSN_GREVI = { 5'b01101, 1'b0, 11'h?, 3'b101, 5'h?, {OPCODE_OP_IMM} }; + // grevi -- pseudo-instructions + parameter logic [31:0] INSN_REV_P = + { 5'b01101, 1'b0, 1'b?, 5'b00001, 5'h?, 3'b101, 5'h?, {OPCODE_OP_IMM} }; + parameter logic [31:0] INSN_REV2_N = + { 5'b01101, 1'b0, 1'b?, 5'b00010, 5'h?, 3'b101, 5'h?, {OPCODE_OP_IMM} }; + parameter logic [31:0] INSN_REV_N = + { 5'b01101, 1'b0, 1'b?, 5'b00011, 5'h?, 3'b101, 5'h?, {OPCODE_OP_IMM} }; + parameter logic [31:0] INSN_REV4_B = + { 5'b01101, 1'b0, 1'b?, 5'b00100, 5'h?, 3'b101, 5'h?, {OPCODE_OP_IMM} }; + parameter logic [31:0] INSN_REV2_B = + { 5'b01101, 1'b0, 1'b?, 5'b00110, 5'h?, 3'b101, 5'h?, {OPCODE_OP_IMM} }; + parameter logic [31:0] INSN_REV_B = + { 5'b01101, 1'b0, 1'b?, 5'b00111, 5'h?, 3'b101, 5'h?, {OPCODE_OP_IMM} }; + parameter logic [31:0] INSN_REV8_H = + { 5'b01101, 1'b0, 1'b?, 5'b01000, 5'h?, 3'b101, 5'h?, {OPCODE_OP_IMM} }; + parameter logic [31:0] INSN_REV4_H = + { 5'b01101, 1'b0, 1'b?, 5'b01100, 5'h?, 3'b101, 5'h?, {OPCODE_OP_IMM} }; + parameter logic [31:0] INSN_REV2_H = + { 5'b01101, 1'b0, 1'b?, 5'b01110, 5'h?, 3'b101, 5'h?, {OPCODE_OP_IMM} }; + parameter logic [31:0] INSN_REV_H = + { 5'b01101, 1'b0, 1'b?, 5'b01111, 5'h?, 3'b101, 5'h?, {OPCODE_OP_IMM} }; + parameter logic [31:0] INSN_REV16 = + { 5'b01101, 1'b0, 1'b?, 5'b10000, 5'h?, 3'b101, 5'h?, {OPCODE_OP_IMM} }; + parameter logic [31:0] INSN_REV8 = + { 5'b01101, 1'b0, 1'b?, 5'b11000, 5'h?, 3'b101, 5'h?, {OPCODE_OP_IMM} }; + parameter logic [31:0] INSN_REV4 = + { 5'b01101, 1'b0, 1'b?, 5'b11100, 5'h?, 3'b101, 5'h?, {OPCODE_OP_IMM} }; + parameter logic [31:0] INSN_REV2 = + { 5'b01101, 1'b0, 1'b?, 5'b11110, 5'h?, 3'b101, 5'h?, {OPCODE_OP_IMM} }; + parameter logic [31:0] INSN_REV = + { 5'b01101, 1'b0, 1'b?, 5'b11111, 5'h?, 3'b101, 5'h?, {OPCODE_OP_IMM} }; + // gorci + // Only log2(XLEN) bits of the immediate are used. For RV32, this means only the bits in + // instr[24:20] are effectively used. Whenever instr[26] is set, gorci is instead decoded as fsri. + parameter logic [31:0] INSN_GORCI = { 5'b00101, 1'b0, 11'h?, 3'b101, 5'h?, {OPCODE_OP_IMM} }; + // gorci -- pseudo-instructions + parameter logic [31:0] INSN_ORC_P = + { 5'b00101, 1'b0, 1'b?, 5'b00001, 5'h?, 3'b101, 5'h?, {OPCODE_OP_IMM} }; + parameter logic [31:0] INSN_ORC2_N = + { 5'b00101, 1'b0, 1'b?, 5'b00010, 5'h?, 3'b101, 5'h?, {OPCODE_OP_IMM} }; + parameter logic [31:0] INSN_ORC_N = + { 5'b00101, 1'b0, 1'b?, 5'b00011, 5'h?, 3'b101, 5'h?, {OPCODE_OP_IMM} }; + parameter logic [31:0] INSN_ORC4_B = + { 5'b00101, 1'b0, 1'b?, 5'b00100, 5'h?, 3'b101, 5'h?, {OPCODE_OP_IMM} }; + parameter logic [31:0] INSN_ORC2_B = + { 5'b00101, 1'b0, 1'b?, 5'b00110, 5'h?, 3'b101, 5'h?, {OPCODE_OP_IMM} }; + parameter logic [31:0] INSN_ORC_B = + { 5'b00101, 1'b0, 1'b?, 5'b00111, 5'h?, 3'b101, 5'h?, {OPCODE_OP_IMM} }; + parameter logic [31:0] INSN_ORC8_H = + { 5'b00101, 1'b0, 1'b?, 5'b01000, 5'h?, 3'b101, 5'h?, {OPCODE_OP_IMM} }; + parameter logic [31:0] INSN_ORC4_H = + { 5'b00101, 1'b0, 1'b?, 5'b01100, 5'h?, 3'b101, 5'h?, {OPCODE_OP_IMM} }; + parameter logic [31:0] INSN_ORC2_H = + { 5'b00101, 1'b0, 1'b?, 5'b01110, 5'h?, 3'b101, 5'h?, {OPCODE_OP_IMM} }; + parameter logic [31:0] INSN_ORC_H = + { 5'b00101, 1'b0, 1'b?, 5'b01111, 5'h?, 3'b101, 5'h?, {OPCODE_OP_IMM} }; + parameter logic [31:0] INSN_ORC16 = + { 5'b00101, 1'b0, 1'b?, 5'b10000, 5'h?, 3'b101, 5'h?, {OPCODE_OP_IMM} }; + parameter logic [31:0] INSN_ORC8 = + { 5'b00101, 1'b0, 1'b?, 5'b11000, 5'h?, 3'b101, 5'h?, {OPCODE_OP_IMM} }; + parameter logic [31:0] INSN_ORC4 = + { 5'b00101, 1'b0, 1'b?, 5'b11100, 5'h?, 3'b101, 5'h?, {OPCODE_OP_IMM} }; + parameter logic [31:0] INSN_ORC2 = + { 5'b00101, 1'b0, 1'b?, 5'b11110, 5'h?, 3'b101, 5'h?, {OPCODE_OP_IMM} }; + parameter logic [31:0] INSN_ORC = + { 5'b00101, 1'b0, 1'b?, 5'b11111, 5'h?, 3'b101, 5'h?, {OPCODE_OP_IMM} }; + // shfli + parameter logic [31:0] INSN_SHFLI = { 6'b000010, 11'h?, 3'b001, 5'h?, {OPCODE_OP_IMM} }; + // shfli -- pseudo-instructions + parameter logic [31:0] INSN_ZIP_N = + { 6'b000010, 2'h?, 4'b0001, 5'h?, 3'b001, 5'h?, {OPCODE_OP_IMM} }; + parameter logic [31:0] INSN_ZIP2_B = + { 6'b000010, 2'h?, 4'b0010, 5'h?, 3'b001, 5'h?, {OPCODE_OP_IMM} }; + parameter logic [31:0] INSN_ZIP_B = + { 6'b000010, 2'h?, 4'b0011, 5'h?, 3'b001, 5'h?, {OPCODE_OP_IMM} }; + parameter logic [31:0] INSN_ZIP4_H = + { 6'b000010, 2'h?, 4'b0100, 5'h?, 3'b001, 5'h?, {OPCODE_OP_IMM} }; + parameter logic [31:0] INSN_ZIP2_H = + { 6'b000010, 2'h?, 4'b0110, 5'h?, 3'b001, 5'h?, {OPCODE_OP_IMM} }; + parameter logic [31:0] INSN_ZIP_H = + { 6'b000010, 2'h?, 4'b0111, 5'h?, 3'b001, 5'h?, {OPCODE_OP_IMM} }; + parameter logic [31:0] INSN_ZIP8 = + { 6'b000010, 2'h?, 4'b1000, 5'h?, 3'b001, 5'h?, {OPCODE_OP_IMM} }; + parameter logic [31:0] INSN_ZIP4 = + { 6'b000010, 2'h?, 4'b1100, 5'h?, 3'b001, 5'h?, {OPCODE_OP_IMM} }; + parameter logic [31:0] INSN_ZIP2 = + { 6'b000010, 2'h?, 4'b1110, 5'h?, 3'b001, 5'h?, {OPCODE_OP_IMM} }; + parameter logic [31:0] INSN_ZIP = + { 6'b000010, 2'h?, 4'b1111, 5'h?, 3'b001, 5'h?, {OPCODE_OP_IMM} }; + // unshfli + parameter logic [31:0] INSN_UNSHFLI = { 6'b000010, 11'h?, 3'b101, 5'h?, {OPCODE_OP_IMM} }; + // unshfli -- pseudo-instructions + parameter logic [31:0] INSN_UNZIP_N = + { 6'b000010, 2'h?, 4'b0001, 5'h?, 3'b101, 5'h?, {OPCODE_OP_IMM} }; + parameter logic [31:0] INSN_UNZIP2_B = + { 6'b000010, 2'h?, 4'b0010, 5'h?, 3'b101, 5'h?, {OPCODE_OP_IMM} }; + parameter logic [31:0] INSN_UNZIP_B = + { 6'b000010, 2'h?, 4'b0011, 5'h?, 3'b101, 5'h?, {OPCODE_OP_IMM} }; + parameter logic [31:0] INSN_UNZIP4_H = + { 6'b000010, 2'h?, 4'b0100, 5'h?, 3'b101, 5'h?, {OPCODE_OP_IMM} }; + parameter logic [31:0] INSN_UNZIP2_H = + { 6'b000010, 2'h?, 4'b0110, 5'h?, 3'b101, 5'h?, {OPCODE_OP_IMM} }; + parameter logic [31:0] INSN_UNZIP_H = + { 6'b000010, 2'h?, 4'b0111, 5'h?, 3'b101, 5'h?, {OPCODE_OP_IMM} }; + parameter logic [31:0] INSN_UNZIP8 = + { 6'b000010, 2'h?, 4'b1000, 5'h?, 3'b101, 5'h?, {OPCODE_OP_IMM} }; + parameter logic [31:0] INSN_UNZIP4 = + { 6'b000010, 2'h?, 4'b1100, 5'h?, 3'b101, 5'h?, {OPCODE_OP_IMM} }; + parameter logic [31:0] INSN_UNZIP2 = + { 6'b000010, 2'h?, 4'b1110, 5'h?, 3'b101, 5'h?, {OPCODE_OP_IMM} }; + parameter logic [31:0] INSN_UNZIP = + { 6'b000010, 2'h?, 4'b1111, 5'h?, 3'b101, 5'h?, {OPCODE_OP_IMM} }; -parameter logic [31:0] INSN_GREV = { 7'b0110100, 10'h?, 3'b101, 5'h?, {OPCODE_OP} }; -parameter logic [31:0] INSN_GORC = { 7'b0010100, 10'h?, 3'b101, 5'h?, {OPCODE_OP} }; -parameter logic [31:0] INSN_SHFL = { 7'b0000100, 10'h?, 3'b001, 5'h?, {OPCODE_OP} }; -parameter logic [31:0] INSN_UNSHFL = { 7'b0000100, 10'h?, 3'b101, 5'h?, {OPCODE_OP} }; + parameter logic [31:0] INSN_GREV = { 7'b0110100, 10'h?, 3'b101, 5'h?, {OPCODE_OP} }; + parameter logic [31:0] INSN_GORC = { 7'b0010100, 10'h?, 3'b101, 5'h?, {OPCODE_OP} }; + parameter logic [31:0] INSN_SHFL = { 7'b0000100, 10'h?, 3'b001, 5'h?, {OPCODE_OP} }; + parameter logic [31:0] INSN_UNSHFL = { 7'b0000100, 10'h?, 3'b101, 5'h?, {OPCODE_OP} }; -// ZBE -parameter logic [31:0] INSN_BDEP = {7'b0100100, 10'h?, 3'b110, 5'h?, {OPCODE_OP} }; -parameter logic [31:0] INSN_BEXT = {7'b0000100, 10'h?, 3'b110, 5'h?, {OPCODE_OP} }; + // ZBE + parameter logic [31:0] INSN_BDEP = {7'b0100100, 10'h?, 3'b110, 5'h?, {OPCODE_OP} }; + parameter logic [31:0] INSN_BEXT = {7'b0000100, 10'h?, 3'b110, 5'h?, {OPCODE_OP} }; -// ZBT -parameter logic [31:0] INSN_FSRI = { 5'h?, 1'b1, 11'h?, 3'b101, 5'h?, {OPCODE_OP_IMM} }; + // ZBT + parameter logic [31:0] INSN_FSRI = { 5'h?, 1'b1, 11'h?, 3'b101, 5'h?, {OPCODE_OP_IMM} }; -parameter logic [31:0] INSN_CMIX = {5'h?, 2'b11, 10'h?, 3'b001, 5'h?, {OPCODE_OP} }; -parameter logic [31:0] INSN_CMOV = {5'h?, 2'b11, 10'h?, 3'b101, 5'h?, {OPCODE_OP} }; -parameter logic [31:0] INSN_FSL = {5'h?, 2'b10, 10'h?, 3'b001, 5'h?, {OPCODE_OP} }; -parameter logic [31:0] INSN_FSR = {5'h?, 2'b10, 10'h?, 3'b101, 5'h?, {OPCODE_OP} }; + parameter logic [31:0] INSN_CMIX = {5'h?, 2'b11, 10'h?, 3'b001, 5'h?, {OPCODE_OP} }; + parameter logic [31:0] INSN_CMOV = {5'h?, 2'b11, 10'h?, 3'b101, 5'h?, {OPCODE_OP} }; + parameter logic [31:0] INSN_FSL = {5'h?, 2'b10, 10'h?, 3'b001, 5'h?, {OPCODE_OP} }; + parameter logic [31:0] INSN_FSR = {5'h?, 2'b10, 10'h?, 3'b101, 5'h?, {OPCODE_OP} }; -// ZBF -parameter logic [31:0] INSN_BFP = {7'b0100100, 10'h?, 3'b111, 5'h?, {OPCODE_OP} }; + // ZBF + parameter logic [31:0] INSN_BFP = {7'b0100100, 10'h?, 3'b111, 5'h?, {OPCODE_OP} }; -// ZBC -parameter logic [31:0] INSN_CLMUL = {7'b0000101, 10'h?, 3'b001, 5'h?, {OPCODE_OP} }; -parameter logic [31:0] INSN_CLMULR = {7'b0000101, 10'h?, 3'b010, 5'h?, {OPCODE_OP} }; -parameter logic [31:0] INSN_CLMULH = {7'b0000101, 10'h?, 3'b011, 5'h?, {OPCODE_OP} }; + // ZBC + parameter logic [31:0] INSN_CLMUL = {7'b0000101, 10'h?, 3'b001, 5'h?, {OPCODE_OP} }; + parameter logic [31:0] INSN_CLMULR = {7'b0000101, 10'h?, 3'b010, 5'h?, {OPCODE_OP} }; + parameter logic [31:0] INSN_CLMULH = {7'b0000101, 10'h?, 3'b011, 5'h?, {OPCODE_OP} }; -// ZBR -parameter logic [31:0] INSN_CRC32_B = {7'b0110000, 5'b10000, 5'h?, 3'b001, 5'h?, {OPCODE_OP_IMM} }; -parameter logic [31:0] INSN_CRC32_H = {7'b0110000, 5'b10001, 5'h?, 3'b001, 5'h?, {OPCODE_OP_IMM} }; -parameter logic [31:0] INSN_CRC32_W = {7'b0110000, 5'b10010, 5'h?, 3'b001, 5'h?, {OPCODE_OP_IMM} }; -parameter logic [31:0] INSN_CRC32C_B = {7'b0110000, 5'b11000, 5'h?, 3'b001, 5'h?, {OPCODE_OP_IMM} }; -parameter logic [31:0] INSN_CRC32C_H = {7'b0110000, 5'b11001, 5'h?, 3'b001, 5'h?, {OPCODE_OP_IMM} }; -parameter logic [31:0] INSN_CRC32C_W = {7'b0110000, 5'b11010, 5'h?, 3'b001, 5'h?, {OPCODE_OP_IMM} }; + // ZBR + parameter logic [31:0] INSN_CRC32_B = + {7'b0110000, 5'b10000, 5'h?, 3'b001, 5'h?, {OPCODE_OP_IMM} }; + parameter logic [31:0] INSN_CRC32_H = + {7'b0110000, 5'b10001, 5'h?, 3'b001, 5'h?, {OPCODE_OP_IMM} }; + parameter logic [31:0] INSN_CRC32_W = + {7'b0110000, 5'b10010, 5'h?, 3'b001, 5'h?, {OPCODE_OP_IMM} }; + parameter logic [31:0] INSN_CRC32C_B = + {7'b0110000, 5'b11000, 5'h?, 3'b001, 5'h?, {OPCODE_OP_IMM} }; + parameter logic [31:0] INSN_CRC32C_H = + {7'b0110000, 5'b11001, 5'h?, 3'b001, 5'h?, {OPCODE_OP_IMM} }; + parameter logic [31:0] INSN_CRC32C_W = + {7'b0110000, 5'b11010, 5'h?, 3'b001, 5'h?, {OPCODE_OP_IMM} }; -// LOAD & STORE -parameter logic [31:0] INSN_LOAD = {25'h?, {OPCODE_LOAD } }; -parameter logic [31:0] INSN_STORE = {25'h?, {OPCODE_STORE} }; + // LOAD & STORE + parameter logic [31:0] INSN_LOAD = {25'h?, {OPCODE_LOAD } }; + parameter logic [31:0] INSN_STORE = {25'h?, {OPCODE_STORE} }; -// MISC-MEM -parameter logic [31:0] INSN_FENCE = { 17'h?, 3'b000, 5'h?, {OPCODE_MISC_MEM} }; -parameter logic [31:0] INSN_FENCEI = { 17'h0, 3'b001, 5'h0, {OPCODE_MISC_MEM} }; + // MISC-MEM + parameter logic [31:0] INSN_FENCE = { 17'h?, 3'b000, 5'h?, {OPCODE_MISC_MEM} }; + parameter logic [31:0] INSN_FENCEI = { 17'h0, 3'b001, 5'h0, {OPCODE_MISC_MEM} }; -// Compressed Instructions -// C0 -parameter logic [15:0] INSN_CADDI4SPN = { 3'b000, 11'h?, {OPCODE_C0} }; -parameter logic [15:0] INSN_CLW = { 3'b010, 11'h?, {OPCODE_C0} }; -parameter logic [15:0] INSN_CSW = { 3'b110, 11'h?, {OPCODE_C0} }; + // Compressed Instructions + // C0 + parameter logic [15:0] INSN_CADDI4SPN = { 3'b000, 11'h?, {OPCODE_C0} }; + parameter logic [15:0] INSN_CLW = { 3'b010, 11'h?, {OPCODE_C0} }; + parameter logic [15:0] INSN_CSW = { 3'b110, 11'h?, {OPCODE_C0} }; -// C1 -parameter logic [15:0] INSN_CADDI = { 3'b000, 11'h?, {OPCODE_C1} }; -parameter logic [15:0] INSN_CJAL = { 3'b001, 11'h?, {OPCODE_C1} }; -parameter logic [15:0] INSN_CJ = { 3'b101, 11'h?, {OPCODE_C1} }; -parameter logic [15:0] INSN_CLI = { 3'b010, 11'h?, {OPCODE_C1} }; -parameter logic [15:0] INSN_CLUI = { 3'b011, 11'h?, {OPCODE_C1} }; -parameter logic [15:0] INSN_CBEQZ = { 3'b110, 11'h?, {OPCODE_C1} }; -parameter logic [15:0] INSN_CBNEZ = { 3'b111, 11'h?, {OPCODE_C1} }; -parameter logic [15:0] INSN_CSRLI = { 3'b100, 1'h?, 2'b00, 8'h?, {OPCODE_C1} }; -parameter logic [15:0] INSN_CSRAI = { 3'b100, 1'h?, 2'b01, 8'h?, {OPCODE_C1} }; -parameter logic [15:0] INSN_CANDI = { 3'b100, 1'h?, 2'b10, 8'h?, {OPCODE_C1} }; -parameter logic [15:0] INSN_CSUB = { 3'b100, 1'b0, 2'b11, 3'h?, 2'b00, 3'h?, {OPCODE_C1} }; -parameter logic [15:0] INSN_CXOR = { 3'b100, 1'b0, 2'b11, 3'h?, 2'b01, 3'h?, {OPCODE_C1} }; -parameter logic [15:0] INSN_COR = { 3'b100, 1'b0, 2'b11, 3'h?, 2'b10, 3'h?, {OPCODE_C1} }; -parameter logic [15:0] INSN_CAND = { 3'b100, 1'b0, 2'b11, 3'h?, 2'b11, 3'h?, {OPCODE_C1} }; + // C1 + parameter logic [15:0] INSN_CADDI = { 3'b000, 11'h?, {OPCODE_C1} }; + parameter logic [15:0] INSN_CJAL = { 3'b001, 11'h?, {OPCODE_C1} }; + parameter logic [15:0] INSN_CJ = { 3'b101, 11'h?, {OPCODE_C1} }; + parameter logic [15:0] INSN_CLI = { 3'b010, 11'h?, {OPCODE_C1} }; + parameter logic [15:0] INSN_CLUI = { 3'b011, 11'h?, {OPCODE_C1} }; + parameter logic [15:0] INSN_CBEQZ = { 3'b110, 11'h?, {OPCODE_C1} }; + parameter logic [15:0] INSN_CBNEZ = { 3'b111, 11'h?, {OPCODE_C1} }; + parameter logic [15:0] INSN_CSRLI = { 3'b100, 1'h?, 2'b00, 8'h?, {OPCODE_C1} }; + parameter logic [15:0] INSN_CSRAI = { 3'b100, 1'h?, 2'b01, 8'h?, {OPCODE_C1} }; + parameter logic [15:0] INSN_CANDI = { 3'b100, 1'h?, 2'b10, 8'h?, {OPCODE_C1} }; + parameter logic [15:0] INSN_CSUB = { 3'b100, 1'b0, 2'b11, 3'h?, 2'b00, 3'h?, {OPCODE_C1} }; + parameter logic [15:0] INSN_CXOR = { 3'b100, 1'b0, 2'b11, 3'h?, 2'b01, 3'h?, {OPCODE_C1} }; + parameter logic [15:0] INSN_COR = { 3'b100, 1'b0, 2'b11, 3'h?, 2'b10, 3'h?, {OPCODE_C1} }; + parameter logic [15:0] INSN_CAND = { 3'b100, 1'b0, 2'b11, 3'h?, 2'b11, 3'h?, {OPCODE_C1} }; -// C2 -parameter logic [15:0] INSN_CSLLI = { 3'b000, 11'h?, {OPCODE_C2} }; -parameter logic [15:0] INSN_CLWSP = { 3'b010, 11'h?, {OPCODE_C2} }; -parameter logic [15:0] INSN_SWSP = { 3'b110, 11'h?, {OPCODE_C2} }; -parameter logic [15:0] INSN_CMV = { 3'b100, 1'b0, 10'h?, {OPCODE_C2} }; -parameter logic [15:0] INSN_CADD = { 3'b100, 1'b1, 10'h?, {OPCODE_C2} }; -parameter logic [15:0] INSN_CEBREAK = { 3'b100, 1'b1, 5'h0, 5'h0, {OPCODE_C2} }; -parameter logic [15:0] INSN_CJR = { 3'b100, 1'b0, 5'h0, 5'h0, {OPCODE_C2} }; -parameter logic [15:0] INSN_CJALR = { 3'b100, 1'b1, 5'h?, 5'h0, {OPCODE_C2} }; + // C2 + parameter logic [15:0] INSN_CSLLI = { 3'b000, 11'h?, {OPCODE_C2} }; + parameter logic [15:0] INSN_CLWSP = { 3'b010, 11'h?, {OPCODE_C2} }; + parameter logic [15:0] INSN_SWSP = { 3'b110, 11'h?, {OPCODE_C2} }; + parameter logic [15:0] INSN_CMV = { 3'b100, 1'b0, 10'h?, {OPCODE_C2} }; + parameter logic [15:0] INSN_CADD = { 3'b100, 1'b1, 10'h?, {OPCODE_C2} }; + parameter logic [15:0] INSN_CEBREAK = { 3'b100, 1'b1, 5'h0, 5'h0, {OPCODE_C2} }; + parameter logic [15:0] INSN_CJR = { 3'b100, 1'b0, 5'h0, 5'h0, {OPCODE_C2} }; + parameter logic [15:0] INSN_CJALR = { 3'b100, 1'b1, 5'h?, 5'h0, {OPCODE_C2} }; endpackage