diff --git a/alu.sv b/alu.sv index 51e7a138..d0cdfe73 100644 --- a/alu.sv +++ b/alu.sv @@ -9,9 +9,9 @@ // // // // // Create Date: 19/09/2013 // -// Design Name: Pipelined Processor // +// Design Name: RISC-V processor core // // Module Name: alu.sv // -// Project Name: Processor // +// Project Name: RI5CY // // Language: SystemVerilog // // // // Description: Arithmetic logic unit of the pipelined processor // @@ -25,7 +25,6 @@ // // // // // // -// // //////////////////////////////////////////////////////////////////////////////// `include "defines.sv" diff --git a/compressed_decoder.sv b/compressed_decoder.sv index cb56e9f4..a490bdd5 100644 --- a/compressed_decoder.sv +++ b/compressed_decoder.sv @@ -7,9 +7,9 @@ // // // // // Create Date: 10/06/2015 // -// Design Name: Compressed Instruction Decoder // -// Module Name: id_stage.sv // -// Project Name: RiscV // +// Design Name: Compressed instruction decoder // +// Module Name: compressed_decoder.sv // +// Project Name: RI5CY // // Language: SystemVerilog // // // // Description: Decodes RISC-V compressed instructions into their RV32 // diff --git a/controller.sv b/controller.sv index 52efa12c..78cd15c3 100644 --- a/controller.sv +++ b/controller.sv @@ -6,16 +6,16 @@ // Additional contributions by: // // Igor Loi - igor.loi@unibo.it // // Andreas Traber - atraber@student.ethz.ch // -// // +// Sven Stucki - svstucki@student.ethz.ch // // // // // // Create Date: 19/09/2013 // -// Design Name: Pipelined OpenRISC Processor // +// Design Name: RISC-V processor core // // Module Name: controller.sv // -// Project Name: OR10N // +// Project Name: RI5CY // // Language: SystemVerilog // // // -// Description: CPU Controller of the pipelined processor // +// Description: Main CPU controller of the processor // // // // // // Revision: // diff --git a/cs_registers.sv b/cs_registers.sv index da14efa7..a6541a81 100644 --- a/cs_registers.sv +++ b/cs_registers.sv @@ -7,9 +7,9 @@ // // // // // Create Date: 25/05/2015 // -// Design Name: Pipelined Processor // +// Design Name: RISC-V processor core // // Module Name: cs_registers.sv // -// Project Name: Processor // +// Project Name: RI5CY // // Language: SystemVerilog // // // // Description: Control and Status Registers (CSRs) loosely following the // diff --git a/ex_stage.sv b/ex_stage.sv index 3f2b8cef..ec0e8e68 100644 --- a/ex_stage.sv +++ b/ex_stage.sv @@ -6,22 +6,18 @@ // // // Additional contributions by: // // Igor Loi - igor.loi@unibo.it // +// Sven Stucki - svstucki@student.ethz.ch // // // // // // Create Date: 01/07/2014 // -// Design Name: Execute stage // +// Design Name: Excecute stage // // Module Name: ex_stage.sv // -// Project Name: OR10N // +// Project Name: RI5CY // // Language: SystemVerilog // // // -// Description: Execution stage: Host Alu and Multiplier // +// Description: Execution stage: Hosts ALU and MAC unit // // ALU: computes additions/subtractions/comparisons // -// (in a pure combinational way) // -// Multiplier: // -// 32bit multiplication: takes two cycles to complete. The // -// Result goes to the register file (only the 32 lsb) // -// 64bit multiplication(l.muld): takes two cycles to complete // -// Result goes to sp register maclo(32lsb) and machi(32msb) // +// MAC: // // // // // // Revision: // diff --git a/exc_controller.sv b/exc_controller.sv index 5d9c8dc8..6de41a63 100644 --- a/exc_controller.sv +++ b/exc_controller.sv @@ -6,11 +6,10 @@ // Additional contributions by: // // // // // -// // // Create Date: 20/01/2015 // -// Design Name: Pipelined OpenRISC Processor // +// Design Name: RISC-V processor core // // Module Name: exc_controller.sv // -// Project Name: OR10N // +// Project Name: RI5CY // // Language: SystemVerilog // // // // Description: Exception Controller of the pipelined processor // diff --git a/id_stage.sv b/id_stage.sv index b1fde18e..5fea1dfe 100644 --- a/id_stage.sv +++ b/id_stage.sv @@ -13,7 +13,7 @@ // Create Date: 19/09/2013 // // Design Name: Decode stage // // Module Name: id_stage.sv // -// Project Name: RiscV // +// Project Name: RI5CY // // Language: SystemVerilog // // // // Description: Decode stage of the core. It decodes the instructions // @@ -28,7 +28,6 @@ // // // // // // -// // //////////////////////////////////////////////////////////////////////////////// diff --git a/if_stage.sv b/if_stage.sv index 517bd9ab..5f550569 100644 --- a/if_stage.sv +++ b/if_stage.sv @@ -11,9 +11,9 @@ // // // // // Create Date: 01/07/2014 // -// Design Name: Instruction fetch stage // +// Design Name: RISC-V processor core // // Module Name: if_stage.sv // -// Project Name: RiscV // +// Project Name: RI5CY // // Language: SystemVerilog // // // // Description: Instruction fetch unit: Selection of the next PC, and // @@ -42,8 +42,8 @@ module if_stage // Output of IF Pipeline stage output logic [31:0] instr_rdata_id_o, // read instruction is sampled and sent to ID stage for decoding - output logic [31:0] current_pc_if_o, // "current" pc program counter - output logic [31:0] current_pc_id_o, // current pc program counter + output logic [31:0] current_pc_if_o, // program counter of IF stage + output logic [31:0] current_pc_id_o, // program counter of ID stage // From to Instr memory input logic [31:0] instr_rdata_i, // Instruction read from instruction memory /cache diff --git a/instr_core_interface.sv b/instr_core_interface.sv index 5887abab..e3aac0f1 100644 --- a/instr_core_interface.sv +++ b/instr_core_interface.sv @@ -8,9 +8,9 @@ // // // // // Create Date: 06/08/2014 // -// Design Name: Instruction Fetch interface // +// Design Name: RISC-V processor core // // Module Name: instr_core_interface.sv // -// Project Name: OR10N // +// Project Name: RI5CY // // Language: SystemVerilog // // // // Description: Instruction Fetch interface used to properly handle // @@ -21,8 +21,6 @@ // // // // // // -// // -// // //////////////////////////////////////////////////////////////////////////////// diff --git a/load_store_unit.sv b/load_store_unit.sv index 0133d7d4..9947e882 100644 --- a/load_store_unit.sv +++ b/load_store_unit.sv @@ -10,7 +10,7 @@ // Create Date: 01/07/2014 // // Design Name: Load Store Unit // // Module Name: load_store_unit.sv // -// Project Name: OR10N // +// Project Name: RI5CY // // Language: SystemVerilog // // // // Description: Load Store Unit, used to eliminate multiple access during // @@ -89,7 +89,7 @@ module load_store_unit ///////////////////////////////// BE generation //////////////////////////////// always_comb begin - casex (data_type_ex_i) // Data type 00 Word, 01 Half word, 11,10 byte + case (data_type_ex_i) // Data type 00 Word, 01 Half word, 11,10 byte 2'b00: begin // Writing a word if (misaligned_st == 1'b0) @@ -129,7 +129,8 @@ module load_store_unit end end - 2'b1X: begin // Writing a byte + 2'b10, + 2'b11: begin // Writing a byte case (data_addr_ex_i[1:0]) 2'b00: data_be = 4'b0001; 2'b01: data_be = 4'b0010; @@ -137,7 +138,7 @@ module load_store_unit 2'b11: data_be = 4'b1000; endcase; // case (data_addr_ex_i[1:0]) end - endcase; // casex (data_type_ex_i) + endcase; // case (data_type_ex_i) end // prepare data to be written to the memory diff --git a/mult.sv b/mult.sv index e4b25cab..1bb61585 100644 --- a/mult.sv +++ b/mult.sv @@ -8,17 +8,13 @@ // // // // // Create Date: 19/09/2013 // -// Design Name: Pipelined Processor // +// Design Name: Vectorial Multiplier and MAC // // Module Name: mult.sv // -// Project Name: Processor // +// Project Name: RI5CY // // Language: SystemVerilog // // // -// Description: Multiplier of the pipelined processor // -// Design ware multiplier requires two cycles to complete. // -// Generic multiplier requires only one cycle. result will be // -// stored in a FF. Best synthesis results are achieved with // -// moving the result register in the multiplier with automatic// -// retiming! // +// Description: Advanced MAC unit for PULP. // +// // // // // Revision: // // Revision v0.1 - File Created // diff --git a/register_file.sv b/register_file.sv index b9629b1f..f52254d5 100644 --- a/register_file.sv +++ b/register_file.sv @@ -33,13 +33,6 @@ module riscv_register_file localparam NUM_WORDS = 2**ADDR_WIDTH; - // Read address register, located at the input of the address decoder - logic [ADDR_WIDTH-1:0] RAddrRegxDPa; - logic [ADDR_WIDTH-1:0] RAddrRegxDPb; - logic [ADDR_WIDTH-1:0] RAddrRegxDPc; - logic [NUM_WORDS-1:0] RAddrOneHotxD; - logic [ADDR_WIDTH-1:0] s_raddr_c; - logic [DATA_WIDTH-1:0] MemContentxDP[NUM_WORDS]; logic [NUM_WORDS-1:0] WAddrOneHotxDa; @@ -57,8 +50,6 @@ module riscv_register_file int unsigned i; int unsigned j; int unsigned k; - int unsigned l; - int unsigned m; genvar x; genvar y; diff --git a/riscv_core.sv b/riscv_core.sv index 8f01d41e..4ee681d3 100644 --- a/riscv_core.sv +++ b/riscv_core.sv @@ -797,7 +797,6 @@ module riscv_core // Execution trace generation // synopsys translate_off - /* verilator lint off */ `ifdef TRACE_EXECUTION integer f; string fn; diff --git a/wb_stage.sv b/wb_stage.sv index 7a1220a5..a4484e9d 100644 --- a/wb_stage.sv +++ b/wb_stage.sv @@ -11,7 +11,7 @@ // Create Date: 01/07/2014 // // Design Name: Write Back stage // // Module Name: wb_stage.sv // -// Project Name: OR10N // +// Project Name: RI5CY // // Language: SystemVerilog // // // // Description: Execution stage: hosts a Multiplexer that select data to //