diff --git a/dv/uvm/core_ibex/env/core_ibex_env_cfg.sv b/dv/uvm/core_ibex/env/core_ibex_env_cfg.sv
index fba3b1bb..6231af86 100644
--- a/dv/uvm/core_ibex/env/core_ibex_env_cfg.sv
+++ b/dv/uvm/core_ibex/env/core_ibex_env_cfg.sv
@@ -28,6 +28,9 @@ class core_ibex_env_cfg extends uvm_object;
   // If '1', reaching either threshold fatally ends the test.
   // If '0', we end the test with a pass.
   bit                          is_double_fault_detected_fatal = 1;
+  // If '1', reaching the timeout in seconds fatally ends the test.
+  // If '0', we end the test with a pass.
+  bit                          is_timeout_s_fatal = 1;
 
   `uvm_object_utils_begin(core_ibex_env_cfg)
     `uvm_field_int(enable_double_fault_detector, UVM_DEFAULT)
@@ -50,6 +53,7 @@ class core_ibex_env_cfg extends uvm_object;
     super.new(name);
     void'($value$plusargs("enable_double_fault_detector=%0d", enable_double_fault_detector));
     void'($value$plusargs("is_double_fault_detected_fatal=%0d", is_double_fault_detected_fatal));
+    void'($value$plusargs("is_timeout_s_fatal=%0d", is_timeout_s_fatal));
     void'($value$plusargs("enable_mem_intg_err=%0d", enable_mem_intg_err));
     void'($value$plusargs("enable_irq_single_seq=%0d", enable_irq_single_seq));
     void'($value$plusargs("enable_irq_multiple_seq=%0d", enable_irq_multiple_seq));
diff --git a/dv/uvm/core_ibex/riscv_dv_extension/testlist.yaml b/dv/uvm/core_ibex/riscv_dv_extension/testlist.yaml
index f679e93e..0f8831c5 100644
--- a/dv/uvm/core_ibex/riscv_dv_extension/testlist.yaml
+++ b/dv/uvm/core_ibex/riscv_dv_extension/testlist.yaml
@@ -827,9 +827,11 @@
 - test: riscv_pmp_full_random_test
   desc: >
     Completely randomize the boot mode, mstatus.mprv, and all PMP configuration,
-    and allow PMP regions to overlap.
-    A large number of iterations will be required since this introduces a huge
-    state space of configurations.
+    and allow PMP regions to overlap.  A large number of iterations will be
+    required since this introduces a huge state space of configurations.  Some
+    configurations result in very slow execution as every instruction ends up
+    generating a fault. As this is still a useful test a short timeout with
+    pass on timeout is enabled.
   iterations: 600
   gen_test: riscv_rand_instr_test
   gen_opts: >
@@ -848,6 +850,7 @@
     +enable_unaligned_load_store=1
   sim_opts: >
     +is_double_fault_detected_fatal=0
+    +is_timeout_s_fatal=0
     +enable_bad_intg_on_uninit_access=0
   rtl_test: core_ibex_base_test
   rtl_params:
diff --git a/dv/uvm/core_ibex/tests/core_ibex_base_test.sv b/dv/uvm/core_ibex/tests/core_ibex_base_test.sv
index cd58ffb1..5fe4a23c 100644
--- a/dv/uvm/core_ibex/tests/core_ibex_base_test.sv
+++ b/dv/uvm/core_ibex/tests/core_ibex_base_test.sv
@@ -320,8 +320,15 @@ class core_ibex_base_test extends uvm_test;
           ts = get_unix_timestamp();
           if (ts >= timeout_timestamp) break;
         end
-        `uvm_fatal(`gfn,
-                   $sformatf("Test failed due to wall-clock timeout. [%0ds]", timeout_seconds))
+
+        if (cfg.is_timeout_s_fatal) begin
+          `uvm_fatal(`gfn,
+                     $sformatf("Test failed due to wall-clock timeout. [%0ds]", timeout_seconds))
+        end else begin
+          `uvm_info(`gfn,
+                     $sformatf("Test done due to wall-clock timeout. [%0ds]", timeout_seconds),
+                     UVM_LOW)
+        end
       end
       begin
         wait_for_custom_test_done();