diff --git a/rtl/ibex_register_file_common.sv b/rtl/ibex_register_file_common.sv
index 3f8aa927..38e5bb53 100644
--- a/rtl/ibex_register_file_common.sv
+++ b/rtl/ibex_register_file_common.sv
@@ -8,17 +8,19 @@
  *
  * Register file common security functionality across multiple implementations
  */
+
 module ibex_register_file_common #(
     parameter bit          FPGA          = 0,
     parameter int unsigned AddrWidth     = 5,
     parameter int unsigned NumWords      = 2 ** AddrWidth,
-    parameter int unsigned DataWidth     = 32,
     parameter bit          WrenCheck     = 0,
     parameter bit          RdataMuxCheck = 0
 ) (
+    /* verilator lint_off UNUSED */
     // Clock and Reset
     input logic clk_i,
     input logic rst_ni,
+    /* verilator lint_on UNUSED */
 
     //Read port R1
     input logic [4:0] raddr_a_i,
@@ -81,9 +83,9 @@ module ibex_register_file_common #(
             .err_o (oh_we_err)
         );
     end else begin : gen_no_wren_check
-        if (FPGA == 0) begin : gen_unused_we0_strobe
-            logic unused_strobe;
-            assign unused_strobe = we_onehot_a[0];  // this is never read from in this case
+        if (FPGA) begin : gen_unused_wren_check
+            logic unused_waddr_a;
+            assign unused_waddr_a = ^waddr_a_i;
         end
         assign oh_we_err = 1'b0;
     end
@@ -159,6 +161,11 @@ module ibex_register_file_common #(
     end else begin : gen_no_rdata_mux_check
         assign oh_raddr_a_err = 1'b0;
         assign oh_raddr_b_err = 1'b0;
+        assign raddr_onehot_a = '0;
+        assign raddr_onehot_b = '0;
+
+        logic unused_raddr;
+        assign unused_raddr = ^{raddr_a_i, raddr_b_i};
     end
 
     assign err_o = oh_raddr_a_err || oh_raddr_b_err || oh_we_err;
diff --git a/rtl/ibex_register_file_ff.sv b/rtl/ibex_register_file_ff.sv
index 01be7c17..ce0f6797 100644
--- a/rtl/ibex_register_file_ff.sv
+++ b/rtl/ibex_register_file_ff.sv
@@ -59,7 +59,6 @@ module ibex_register_file_ff #(
     ibex_register_file_common #(
         .AddrWidth(ADDR_WIDTH),
         .NumWords(NUM_WORDS),
-        .DataWidth(DataWidth),
         .WrenCheck(WrenCheck),
         .RdataMuxCheck(RdataMuxCheck)
     ) security_module (
@@ -148,10 +147,21 @@ module ibex_register_file_ff #(
     end else begin : gen_no_rdata_mux_check
         assign rdata_a_o = rf_reg[raddr_a_i];
         assign rdata_b_o = rf_reg[raddr_b_i];
+
+        logic unused_raddr_onehot, unused_oh_raddr_err;
+        assign unused_raddr_onehot = ^{raddr_onehot_a, raddr_onehot_b};
+        assign unused_oh_raddr_err = ^{oh_raddr_a_err, oh_raddr_b_err};
     end
 
     // Signal not used in FF register file
     logic unused_test_en;
     assign unused_test_en = test_en_i;
 
+    if (WrenCheck) begin : gen_wren_check
+    end else begin : gen_unused_wren_check
+        logic unused_strobe, unused_oh_we_err;
+        assign unused_strobe = we_onehot_a[0];  // this is never read from in this case
+        assign unused_oh_we_err = oh_we_err;  // this is never read from in this case
+    end
+
 endmodule
diff --git a/rtl/ibex_register_file_fpga.sv b/rtl/ibex_register_file_fpga.sv
index 3082179a..9ba56a73 100644
--- a/rtl/ibex_register_file_fpga.sv
+++ b/rtl/ibex_register_file_fpga.sv
@@ -61,7 +61,6 @@ module ibex_register_file_fpga #(
         .FPGA(1),
         .AddrWidth(ADDR_WIDTH),
         .NumWords(NUM_WORDS),
-        .DataWidth(DataWidth),
         .WrenCheck(WrenCheck),
         .RdataMuxCheck(RdataMuxCheck)
     ) security_module (
@@ -109,6 +108,10 @@ module ibex_register_file_fpga #(
     end else begin : gen_no_rdata_mux_check
         assign rdata_a_o = (raddr_a_i == '0) ? WordZeroVal : mem[raddr_a_i];
         assign rdata_b_o = (raddr_b_i == '0) ? WordZeroVal : mem[raddr_b_i];
+
+        logic unused_raddr_onehot, unused_oh_raddr_err;
+        assign unused_raddr_onehot = ^{raddr_onehot_a, raddr_onehot_b};
+        assign unused_oh_raddr_err = ^{oh_raddr_a_err, oh_raddr_b_err};
     end
 
     // we select
@@ -143,4 +146,10 @@ module ibex_register_file_fpga #(
     logic unused_test_en;
     assign unused_test_en = test_en_i;
 
+    if (WrenCheck) begin : gen_wren_check
+    end else begin : gen_unused_wren_check
+        logic unused_oh_we_err;
+        assign unused_oh_we_err = oh_we_err;  // this is never read from in this case
+    end
+
 endmodule
diff --git a/rtl/ibex_register_file_latch.sv b/rtl/ibex_register_file_latch.sv
index 8bbbfc86..4818f0dd 100644
--- a/rtl/ibex_register_file_latch.sv
+++ b/rtl/ibex_register_file_latch.sv
@@ -71,7 +71,6 @@ module ibex_register_file_latch #(
     ibex_register_file_common #(
         .AddrWidth(ADDR_WIDTH),
         .NumWords(NUM_WORDS),
-        .DataWidth(DataWidth),
         .WrenCheck(WrenCheck),
         .RdataMuxCheck(RdataMuxCheck)
     ) security_module (
@@ -119,6 +118,10 @@ module ibex_register_file_latch #(
     end else begin : gen_no_rdata_mux_check
         assign rdata_a_o = mem[raddr_a_int];
         assign rdata_b_o = mem[raddr_b_int];
+
+        logic unused_raddr_onehot, unused_oh_raddr_err;
+        assign unused_raddr_onehot = ^{raddr_onehot_a, raddr_onehot_b};
+        assign unused_oh_raddr_err = ^{oh_raddr_a_err, oh_raddr_b_err};
     end
 
     ///////////
@@ -200,6 +203,13 @@ module ibex_register_file_latch #(
         assign mem[0] = WordZeroVal;
     end
 
+    if (WrenCheck) begin : gen_wren_check
+    end else begin : gen_unused_wren_check
+        logic unused_strobe, unused_oh_we_err;
+        assign unused_strobe = we_onehot_a[0];  // this is never read from in this case
+        assign unused_oh_we_err = oh_we_err;  // this is never read from in this case
+    end
+
 `ifdef VERILATOR
     initial begin
         $display("Latch-based register file not supported for Verilator simulation");