diff --git a/dv/uvm/core_ibex/riscv_dv_extension/testlist.yaml b/dv/uvm/core_ibex/riscv_dv_extension/testlist.yaml
index 491011b1..1c6f59dd 100644
--- a/dv/uvm/core_ibex/riscv_dv_extension/testlist.yaml
+++ b/dv/uvm/core_ibex/riscv_dv_extension/testlist.yaml
@@ -407,6 +407,7 @@
   sim_opts: >
     +require_signature_addr=1
     +enable_irq_multiple_seq=1
+    +enable_irq_nmi_seq=1
     +enable_nested_irq=1
   compare_opts:
     compare_final_value_only: 1
diff --git a/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv b/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv
index c4154740..c3bac386 100644
--- a/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv
+++ b/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv
@@ -897,16 +897,16 @@ class core_ibex_nested_irq_test extends core_ibex_directed_test;
     forever begin
       send_irq_stimulus_start(1'b1, 1'b0, valid_irq);
       if (valid_irq) begin
-        initial_irq_delay = vseq.irq_raise_seq_h.max_delay;
-        vseq.irq_raise_seq_h.max_delay = 0;
+        initial_irq_delay = vseq.irq_raise_nmi_seq_h.max_delay;
+        vseq.irq_raise_nmi_seq_h.max_delay = 0;
         // Send nested interrupt after the checks of the first interrupt have finished
         in_nested_trap = 1'b1;
         // wait until we are setting mstatus.mie to 1'b1 to send the next set of interrupts
         wait (csr_vif.csr_cb.csr_access === 1'b1 &&
              csr_vif.csr_cb.csr_addr === CSR_MSTATUS &&
              csr_vif.csr_cb.csr_op != CSR_OP_READ);
-        send_irq_stimulus(1'b0);
-        vseq.irq_raise_seq_h.max_delay = initial_irq_delay;
+        send_nmi_stimulus();
+        vseq.irq_raise_nmi_seq_h.max_delay = initial_irq_delay;
         in_nested_trap = 1'b0;
         send_irq_stimulus_end();
       end