diff --git a/ibex_core.core b/ibex_core.core
index 8c633af8..76596d37 100644
--- a/ibex_core.core
+++ b/ibex_core.core
@@ -41,10 +41,6 @@ filesets:
       - rtl/ibex_core.sv
     file_type: systemVerilogSource
 
-  files_lint:
-    depend:
-      - lowrisc:ibex:sim_shared
-
   files_lint_verilator:
     files:
       - lint/verilator_waiver.vlt: {file_type: vlt}
diff --git a/ibex_core_tracing.core b/ibex_core_tracing.core
index 27864caa..93744693 100644
--- a/ibex_core_tracing.core
+++ b/ibex_core_tracing.core
@@ -13,9 +13,6 @@ filesets:
       - rtl/ibex_core_tracing.sv
     file_type: systemVerilogSource
 
-  files_lint:
-    depend:
-      - lowrisc:ibex:sim_shared
 
   files_lint_verilator:
     files:
@@ -116,7 +113,6 @@ targets:
       # are applied, but not file-specific waivers.
       - tool_verilator ? (files_lint_verilator)
       - files_rtl
-      - files_lint
     parameters:
       - RVFI=true
       - SYNTHESIS=true