diff --git a/zeroriscy_controller.sv b/zeroriscy_controller.sv index 141a9184..0d67eecf 100644 --- a/zeroriscy_controller.sv +++ b/zeroriscy_controller.sv @@ -203,7 +203,6 @@ module zeroriscy_controller // We were just reset, wait for fetch_enable RESET: begin - ctrl_busy_o = 1'b0; instr_req_o = 1'b0; if (fetch_enable_i == 1'b1) @@ -237,7 +236,7 @@ module zeroriscy_controller // instruction in if_stage is already valid SLEEP: begin - // we begin execution when either fetch_enable is high or an + // we begin execution when an // interrupt has arrived ctrl_busy_o = 1'b0; instr_req_o = 1'b0; @@ -248,14 +247,14 @@ module zeroriscy_controller if (dbg_req_i) begin // debug request, now we need to check if we should stay sleeping or // go to normal processing later - if (fetch_enable_i || irq_req_ctrl_i) + if (irq_req_ctrl_i) ctrl_fsm_ns = DBG_SIGNAL; else ctrl_fsm_ns = DBG_SIGNAL_SLEEP; end else begin // no debug request incoming, normal execution flow - if (fetch_enable_i || irq_req_ctrl_i) + if (irq_req_ctrl_i) begin ctrl_fsm_ns = FIRST_FETCH; end @@ -420,7 +419,7 @@ module zeroriscy_controller FLUSH: begin - halt_if_o = fetch_enable_i ? dbg_req_i : 1'b1; + halt_if_o = ~pipe_flush_i ? dbg_req_i : 1'b1; halt_id_o = 1'b1; ctrl_fsm_ns = dbg_req_i ? DBG_SIGNAL : DECODE; @@ -468,7 +467,7 @@ module zeroriscy_controller default:; endcase - if(fetch_enable_i) begin + if(~pipe_flush_i) begin if(dbg_req_i) ctrl_fsm_ns = DBG_SIGNAL; else diff --git a/zeroriscy_core.sv b/zeroriscy_core.sv index a54c6b8f..7daa0423 100644 --- a/zeroriscy_core.sv +++ b/zeroriscy_core.sv @@ -89,7 +89,6 @@ module zeroriscy_core // CPU Control Signals input logic fetch_enable_i, - output logic core_busy_o, input logic [N_EXT_PERF_COUNTERS-1:0] ext_perf_counters_i ); @@ -128,6 +127,9 @@ module zeroriscy_core logic ctrl_busy; logic if_busy; logic lsu_busy; + //core busy signals + logic core_busy; + logic core_ctrl_firstfetch, core_busy_int, core_busy_q; // ALU Control logic [ALU_OP_WIDTH-1:0] alu_operator_ex; @@ -163,7 +165,6 @@ module zeroriscy_core logic [1:0] data_reg_offset_ex; logic data_req_ex; logic [31:0] data_wdata_ex; - logic data_load_event_ex; logic data_misaligned_ex; logic [31:0] regfile_wdata_lsu; @@ -225,8 +226,6 @@ module zeroriscy_core logic perf_branch; logic perf_tbranch; - //core busy signals - logic core_ctrl_firstfetch, core_busy_int, core_busy_q; ////////////////////////////////////////////////////////////////////////////////////////////// // ____ _ _ __ __ _ // @@ -246,9 +245,9 @@ module zeroriscy_core // if we are sleeping on a barrier let's just wait on the instruction // interface to finish loading instructions - assign core_busy_int = (data_load_event_ex & data_req_o) ? if_busy : (if_busy | ctrl_busy | lsu_busy); + assign core_busy_int = if_busy | ctrl_busy | lsu_busy; - always_ff @(posedge clk, negedge rst_ni) + always_ff @(posedge clk_i, negedge rst_ni) begin if (rst_ni == 1'b0) begin core_busy_q <= 1'b0; @@ -257,13 +256,13 @@ module zeroriscy_core end end - assign core_busy_o = core_ctrl_firstfetch ? 1'b1 : core_busy_q; + assign core_busy = core_ctrl_firstfetch ? 1'b1 : core_busy_q; assign dbg_busy = dbg_req | dbg_csr_req | dbg_jump_req | dbg_reg_wreq | debug_req_i; - assign clock_en = clock_en_i | core_busy_o | dbg_busy; + assign clock_en = core_busy | dbg_busy | (irq_i & m_irq_enable); - assign sleeping = (~fetch_enable_i) & (~core_busy_o); + assign sleeping = (~core_busy); // main clock gate of the core @@ -417,7 +416,6 @@ module zeroriscy_core .data_type_ex_o ( data_type_ex ), // to load store unit .data_sign_ext_ex_o ( data_sign_ext_ex ), // to load store unit .data_reg_offset_ex_o ( data_reg_offset_ex ), // to load store unit - .data_load_event_ex_o ( data_load_event_ex ), // to load store unit .data_wdata_ex_o ( data_wdata_ex ), // to load store unit .data_misaligned_i ( data_misaligned ), diff --git a/zeroriscy_decoder.sv b/zeroriscy_decoder.sv index 924432c4..9369f2b1 100644 --- a/zeroriscy_decoder.sv +++ b/zeroriscy_decoder.sv @@ -79,8 +79,6 @@ module zeroriscy_decoder output logic [1:0] data_type_o, // data type on data memory: byte, half word or word output logic data_sign_extension_o, // sign extension on read data from data memory output logic [1:0] data_reg_offset_o, // offset in byte inside register for stores - output logic data_load_event_o, // data request is in the special event range - // jump/branches output logic jump_in_id_o, // jump is being calculated in ALU @@ -136,7 +134,6 @@ module zeroriscy_decoder data_sign_extension_o = 1'b0; data_reg_offset_o = 2'b00; data_req = 1'b0; - data_load_event_o = 1'b0; illegal_insn_o = 1'b0; ebrk_insn_o = 1'b0; @@ -311,10 +308,6 @@ module zeroriscy_decoder endcase end - // special p.elw (event load) - if (instr_rdata_i[14:12] == 3'b110) - data_load_event_o = 1'b1; - if (instr_rdata_i[14:12] == 3'b011) begin // LD -> RV64 only illegal_insn_o = 1'b1; diff --git a/zeroriscy_id_stage.sv b/zeroriscy_id_stage.sv index 420be1b9..e086f32d 100644 --- a/zeroriscy_id_stage.sv +++ b/zeroriscy_id_stage.sv @@ -109,7 +109,6 @@ module zeroriscy_id_stage output logic [1:0] data_type_ex_o, output logic data_sign_ext_ex_o, output logic [1:0] data_reg_offset_ex_o, - output logic data_load_event_ex_o, output logic [31:0] data_wdata_ex_o, input logic data_misaligned_i, @@ -240,7 +239,6 @@ module zeroriscy_id_stage logic data_sign_ext_id; logic [1:0] data_reg_offset_id; logic data_req_id; - logic data_load_event_id; // CSR control logic csr_access; @@ -497,7 +495,6 @@ module zeroriscy_id_stage .data_type_o ( data_type_id ), .data_sign_extension_o ( data_sign_ext_id ), .data_reg_offset_o ( data_reg_offset_id ), - .data_load_event_o ( data_load_event_id ), // jump/branches .jump_in_id_o ( jump_in_id ), @@ -639,7 +636,6 @@ module zeroriscy_id_stage assign data_wdata_ex_o = regfile_data_rb_id; assign data_req_ex_o = data_req_id; assign data_reg_offset_ex_o = data_reg_offset_id; - assign data_load_event_ex_o = data_load_event_id; assign alu_operator_ex_o = alu_operator; assign alu_operand_a_ex_o = alu_operand_a; diff --git a/zeroriscy_int_controller.sv b/zeroriscy_int_controller.sv index c194521d..8c1ab2c0 100644 --- a/zeroriscy_int_controller.sv +++ b/zeroriscy_int_controller.sv @@ -45,7 +45,7 @@ module zeroriscy_int_controller input logic m_IE_i // interrupt enable bit from CSR (M mode) ); - enum logic [1:0] { IDLE, IRQ_PENDING, IRQ_DONE} exc_ctrl_cs, exc_ctrl_ns; + enum logic [1:0] { IDLE, IRQ_PENDING, IRQ_DONE} exc_ctrl_cs; logic irq_enable_ext; logic [4:0] irq_id_q; diff --git a/zeroriscy_tracer.sv b/zeroriscy_tracer.sv index ccc2beba..14a119b8 100644 --- a/zeroriscy_tracer.sv +++ b/zeroriscy_tracer.sv @@ -331,7 +331,7 @@ module zeroriscy_tracer instr_trace_t trace; mem_acc_t mem_acc; // special case for WFI because we don't wait for unstalling there - if ((id_valid && is_decoding) || pipe_flush || (ex_data_req && is_decoding)) + if ((id_valid || pipe_flush || ex_data_req) && is_decoding) begin trace = new ();