diff --git a/decoder.sv b/decoder.sv
index 2e3ac157..db3ed854 100644
--- a/decoder.sv
+++ b/decoder.sv
@@ -323,8 +323,8 @@ module riscv_decoder
         `ifdef NO_JUMP_ADDER
         jump_in_id          = BRANCH_JALR;
         // Calculate jump target in EX
-        alu_op_a_mux_sel_o  = OP_A_CURRPC;
-        alu_op_b_mux_sel_o  = OP_B_REGA_OR_FWD;
+        alu_op_a_mux_sel_o  = OP_A_REGA_OR_FWD;
+        alu_op_b_mux_sel_o  = OP_B_ZERO;
         imm_b_mux_sel_o     = IMMB_SB;
         alu_operator_o      = ALU_ADD;
         regfile_alu_we      = 1'b1;
diff --git a/id_stage.sv b/id_stage.sv
index c585ed75..ea2f0ab6 100644
--- a/id_stage.sv
+++ b/id_stage.sv
@@ -848,6 +848,10 @@ module riscv_id_stage
         `endif // THREE_PORT_REG_FILE
         OP_B_IMM:          operand_b = imm_b;
         OP_B_BMASK:        operand_b = $unsigned(operand_b_fw_id[4:0]);
+        // CONFIG_REGION: NO_JUMP_ADDER
+        `ifdef NO_JUMP_ADDER
+        OP_B_ZERO:         operand_b = '0;
+        `endif
         default:           operand_b = operand_b_fw_id;
       endcase // case (alu_op_b_mux_sel)
   	end
diff --git a/include/riscv_defines.sv b/include/riscv_defines.sv
index ac0299e6..d7b83c56 100644
--- a/include/riscv_defines.sv
+++ b/include/riscv_defines.sv
@@ -227,6 +227,7 @@ parameter OP_B_REGC_OR_FWD = 3'b001;
 parameter OP_B_IMM         = 3'b010;
 parameter OP_B_REGA_OR_FWD = 3'b011;
 parameter OP_B_BMASK       = 3'b100;
+parameter OP_B_ZERO        = 3'b101;
 
 // immediate b selection
 parameter IMMB_I      = 4'b0000;