From cb01156154e3c3e64c7edb14d5dd37a3dab541dc Mon Sep 17 00:00:00 2001 From: Greg Chadwick Date: Sat, 29 Oct 2022 10:38:27 +0100 Subject: [PATCH] [cov] Add illegal bin for misaligned data accesses --- dv/uvm/core_ibex/fcov/core_ibex_fcov_if.sv | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/dv/uvm/core_ibex/fcov/core_ibex_fcov_if.sv b/dv/uvm/core_ibex/fcov/core_ibex_fcov_if.sv index b09421b0..1fefe462 100644 --- a/dv/uvm/core_ibex/fcov/core_ibex_fcov_if.sv +++ b/dv/uvm/core_ibex/fcov/core_ibex_fcov_if.sv @@ -565,7 +565,12 @@ interface core_ibex_fcov_if import ibex_pkg::*; ( (load_store_unit_i.fcov_mis_rvalid_2); misaligned_data_bus_err_cross: cross cp_misaligned_first_data_bus_err, - cp_misaligned_second_data_bus_err; + cp_misaligned_second_data_bus_err { + // Cannot see both bus errors together as they're signalled at different states of the load + // store unit FSM + illegal_bins illegal = binsof(cp_misaligned_first_data_bus_err) intersect {1'b1} && + binsof(cp_misaligned_second_data_bus_err) intersect {1'b1}; + } misaligned_insn_bus_err_cross: cross id_stage_i.instr_fetch_err_i, id_stage_i.instr_fetch_err_plus2_i;