diff --git a/cs_registers.sv b/cs_registers.sv
index 72c22e84..040aa91e 100644
--- a/cs_registers.sv
+++ b/cs_registers.sv
@@ -364,9 +364,9 @@ module riscv_cs_registers
     if (is_pcer) begin
       unique case (csr_op_i)
         `CSR_OP_NONE:   ;
-        `CSR_OP_WRITE:  PCER_n = csr_wdata_i[N_PERF_REGS-1:0];
-        `CSR_OP_SET:    PCER_n = csr_wdata_i[N_PERF_REGS-1:0] | PCER_q;
-        `CSR_OP_CLEAR:  PCER_n = csr_wdata_i[N_PERF_REGS-1:0] & ~(PCER_q);
+        `CSR_OP_WRITE:  PCER_n = csr_wdata_i[N_PERF_COUNTERS-1:0];
+        `CSR_OP_SET:    PCER_n = csr_wdata_i[N_PERF_COUNTERS-1:0] | PCER_q;
+        `CSR_OP_CLEAR:  PCER_n = csr_wdata_i[N_PERF_COUNTERS-1:0] & ~(PCER_q);
       endcase
     end
   end
@@ -378,7 +378,7 @@ module riscv_cs_registers
     begin
       id_valid_q <= 1'b0;
 
-      PCER_q <= 'h0;
+      PCER_q <= '0;
       PCMR_q <= 2'h3;
 
       for(int i = 0; i < N_PERF_REGS; i++)
diff --git a/debug_unit.sv b/debug_unit.sv
index f0630ae4..a4e5f709 100644
--- a/debug_unit.sv
+++ b/debug_unit.sv
@@ -150,7 +150,7 @@ module riscv_debug_unit
     DSR_DN             = DSR_DP;
     dbginf_data_o      = 32'b0;
     regfile_we_o       = 1'b0;
-    regfile_addr_o     = 'h0;
+    regfile_addr_o     = '0;
     regfile_mux_o      = 1'b0;
     sp_mux_o           = 1'b0;
     set_npc_o          = 1'b0;
@@ -268,7 +268,7 @@ module riscv_debug_unit
   begin
     if (rst_n == 1'b0) begin
       DMR1_DP            <= 2'b0;
-      DSR_DP             <= 'b0;
+      DSR_DP             <= '0;
       BP_State_SP        <= Idle;
       pc_tracking_fsm_cs <= IFID;
     end