diff --git a/examples/simple_system/README.md b/examples/simple_system/README.md
index 50f6629c..0b865fce 100644
--- a/examples/simple_system/README.md
+++ b/examples/simple_system/README.md
@@ -92,6 +92,26 @@ The simulator produces several output files
 * ibex_simple_system_pcount.csv - A csv of the performance counters
 * trace_core_00000000.log - An instruction trace of execution
 
+## Simulating with Synopsys VCS
+
+Similar to the Verilator flow the Simple System simulator binary can be built using:
+
+```
+fusesoc --cores-root=. run --target=sim --tool=vcs --setup --build lowrisc:ibex:ibex_simple_system --RV32M=1 --RV32E=0 --SRAM_INIT_FILE=`<sw_vmem_file>`
+```
+
+`<sw_vmem_file>` should be a path to a vmem file built as described above, use
+./examples/sw/simple_system/hello_test/hello_test.vmem to run the hello_test
+binary.
+
+To run the simulator:
+
+```
+./build/lowrisc_ibex_ibex_simple_system_0/sim-vcs/lowrisc_ibex_ibex_simple_system_0
+```
+
+Pass `-gui` to use the DVE GUI.
+
 ## System Memory Map
 
 | Address             | Description                                                                                            |
diff --git a/examples/simple_system/ibex_simple_system.core b/examples/simple_system/ibex_simple_system.core
index 6cf76682..9cc8b7a4 100644
--- a/examples/simple_system/ibex_simple_system.core
+++ b/examples/simple_system/ibex_simple_system.core
@@ -27,6 +27,10 @@ parameters:
     paramtype: vlogparam
     default: 0
     description: Enable the E ISA extension (reduced register set) [0/1]
+  SRAM_INIT_FILE:
+    datatype: str
+    paramtype: vlogdefine
+    descriptions: Path to a vmem file to initialize the RAM with
 
 targets:
   sim:
@@ -36,8 +40,12 @@ targets:
     parameters:
       - RV32M
       - RV32E
+      - SRAM_INIT_FILE
     toplevel: ibex_simple_system
     tools:
+      vcs:
+        vcs_options:
+          - '-debug_access+r'
       verilator:
         mode: cc
         verilator_options:
diff --git a/examples/simple_system/rtl/ibex_simple_system.sv b/examples/simple_system/rtl/ibex_simple_system.sv
index 80dafc5c..79651a9f 100644
--- a/examples/simple_system/rtl/ibex_simple_system.sv
+++ b/examples/simple_system/rtl/ibex_simple_system.sv
@@ -21,10 +21,7 @@ module ibex_simple_system (
   parameter bit RV32E = 0;
   parameter bit RV32M = 1;
 
-  logic clk_sys, rst_sys_n;
-
-  assign clk_sys = IO_CLK;
-  assign rst_sys_n = IO_RST_N;
+  logic clk_sys = 1'b0, rst_sys_n;
 
   typedef enum {
     CoreD,
@@ -69,6 +66,22 @@ module ibex_simple_system (
   assign cfg_device_addr_mask[SimCtrl] = ~32'h3FF; // 1 kB
 
 
+  `ifdef VERILATOR
+    assign clk_sys = IO_CLK;
+    assign rst_sys_n = IO_RST_N;
+  `else
+    initial begin
+      rst_sys_n = 1'b0;
+      device_err = '{default:1'b0};
+      #8
+      rst_sys_n = 1'b1;
+    end
+    always begin
+      #1 clk_sys = 1'b0;
+      #1 clk_sys = 1'b1;
+    end
+  `endif
+
   bus #(
     .NrDevices   (NrDevices),
     .NrHosts     (NrHosts  ),
diff --git a/shared/rtl/sim/simulator_ctrl.sv b/shared/rtl/sim/simulator_ctrl.sv
index 002845a4..555025e7 100644
--- a/shared/rtl/sim/simulator_ctrl.sv
+++ b/shared/rtl/sim/simulator_ctrl.sv
@@ -36,7 +36,7 @@ module simulator_ctrl #(
   localparam SIM_CTRL_ADDR = 1;
 
   logic [7:0] ctrl_addr;
-  logic [2:0] sim_finish;
+  logic [2:0] sim_finish = 3'b000;
 
   integer log_fd;
 
@@ -78,9 +78,7 @@ module simulator_ctrl #(
         endcase
       end
     end
-  end
 
-  always_ff @(posedge clk_i or negedge rst_ni) begin
     if (sim_finish != 'b0) begin
       sim_finish <= sim_finish + 1;
     end
@@ -88,6 +86,7 @@ module simulator_ctrl #(
       $finish;
     end
   end
+
   assign rdata_o = '0;
 endmodule