diff --git a/alu.sv b/alu.sv index d0cdfe73..157444b3 100644 --- a/alu.sv +++ b/alu.sv @@ -35,9 +35,6 @@ module alu input logic [`ALU_OP_WIDTH-1:0] operator_i, input logic [31:0] operand_a_i, input logic [31:0] operand_b_i, - input logic [31:0] operand_c_i, - input logic carry_i, - input logic flag_i, input logic [1:0] vector_mode_i, input logic [1:0] cmp_mode_i, @@ -95,8 +92,6 @@ module alu carry_in = {carry_out[2], carry_out[1], carry_out[0], 1'b0}; case (operator_i) - `ALU_ADDC: carry_in[0] = carry_i; - `ALU_SUB, `ALU_ABS: begin case (vector_mode_i) @@ -391,9 +386,6 @@ module alu begin sel_minmax[3:0] = is_greater ^ {4{do_min}}; - if(operator_i == `ALU_CMOV) - sel_minmax[3:0] = {4{flag_i}}; - if(operator_i == `ALU_INS) begin if(vector_mode_i == `VEC_MODE16) @@ -557,7 +549,7 @@ module alu unique case (operator_i) // Standard Operations - `ALU_ADD, `ALU_ADDC, `ALU_SUB: + `ALU_ADD, `ALU_SUB: begin // Addition defined above result_o = adder_result[31:0]; carry_o = carry_out[3]; @@ -587,8 +579,8 @@ module alu `ALU_EXTWZ, `ALU_EXTWS: result_o = operand_a_i; `ALU_EXTBZ, `ALU_EXTBS, `ALU_EXTHZ, `ALU_EXTHS, `ALU_EXT: result_o = result_ext; - // Min/Max/Abs, CMOV, INS - `ALU_MIN, `ALU_MINU, `ALU_MAX, `ALU_MAXU, `ALU_ABS, `ALU_CMOV, `ALU_INS: result_o = result_minmax; + // Min/Max/Abs, INS + `ALU_MIN, `ALU_MINU, `ALU_MAX, `ALU_MAXU, `ALU_ABS, `ALU_INS: result_o = result_minmax; // Comparison Operations `ALU_EQ, `ALU_NE, `ALU_GTU, `ALU_GEU, `ALU_LTU, `ALU_LEU, `ALU_GTS, `ALU_GES, `ALU_LTS, `ALU_LES: diff --git a/compressed_decoder.sv b/compressed_decoder.sv index 3d48f20a..1da4ab0a 100644 --- a/compressed_decoder.sv +++ b/compressed_decoder.sv @@ -28,7 +28,6 @@ module compressed_decoder ( input logic [31:0] instr_i, output logic [31:0] instr_o, - output logic is_compressed_o, output logic illegal_instr_o ); @@ -44,7 +43,6 @@ module compressed_decoder always_comb begin illegal_instr_o = 1'b0; - is_compressed_o = 1'b1; instr_o = '0; unique case (instr_i[1:0]) @@ -260,7 +258,6 @@ module compressed_decoder 2'b11: begin // 32 bit (or more) instruction instr_o = instr_i; - is_compressed_o = 1'b0; end endcase end diff --git a/controller.sv b/controller.sv index 15b8a3f0..6aa72db1 100644 --- a/controller.sv +++ b/controller.sv @@ -39,8 +39,6 @@ module controller input logic fetch_enable_i, // Start the decoding output logic core_busy_o, // Core is busy processing instructions - output logic force_nop_o, - input logic [31:0] instr_rdata_i, // Instruction read from instr memory/cache: (sampled in the if stage) output logic instr_req_o, // Fetch instruction Request: input logic instr_gnt_i, // grant from icache @@ -50,7 +48,6 @@ module controller // ALU signals output logic [`ALU_OP_WIDTH-1:0] alu_operator_o, // Operator in the Ex stage for the ALU block - output logic extend_immediate_o, // Extend a 16 bit immediate to 32 bit output logic [1:0] alu_op_a_mux_sel_o, // Operator a is selected between reg value, PC or immediate output logic [1:0] alu_op_b_mux_sel_o, // Operator b is selected between reg value or immediate output logic alu_op_c_mux_sel_o, // Operator c is selected between reg value or PC @@ -64,7 +61,6 @@ module controller output logic mult_en_o, // Multiplication operation is running output logic [1:0] mult_sel_subword_o, // Select subwords for 16x16 bit of multiplier output logic [1:0] mult_signed_mode_o, // Multiplication in signed mode - output logic mult_use_carry_o, // Use carry for MAC output logic mult_mac_en_o, // Use the accumulator after multiplication output logic regfile_we_o, // Write Enable to regfile @@ -113,9 +109,6 @@ module controller input logic dbg_set_npc_i, // Change PC to value from debug unit output logic dbg_trap_o, // trap hit, inform debug unit - // CSR Signals - output logic restore_sr_o, // restores status register after interrupt - // Forwarding signals from regfile input logic [4:0] regfile_waddr_ex_i, // FW: write address from EX stage input logic regfile_we_ex_i, // FW: write enable from EX stage @@ -200,7 +193,6 @@ module controller jump_in_id = `BRANCH_NONE; alu_operator = `ALU_NOP; - extend_immediate_o = 1'b0; alu_op_a_mux_sel_o = `OP_A_REGA_OR_FWD; alu_op_b_mux_sel_o = `OP_B_REGB_OR_FWD; alu_op_c_mux_sel_o = `OP_C_REGC_OR_FWD; @@ -212,7 +204,6 @@ module controller mult_en = 1'b0; mult_signed_mode_o = 2'b00; mult_sel_subword_o = 2'b00; - mult_use_carry_o = 1'b0; mult_mac_en_o = 1'b0; regfile_we = 1'b0; @@ -235,7 +226,6 @@ module controller data_reg_offset_o = 2'b00; data_req = 1'b0; - restore_sr_o = 1'b0; clear_isr_running_o = 1'b0; illegal_insn_int = 1'b0; @@ -1253,10 +1243,6 @@ module controller assign jump_in_id_o = (deassert_we) ? `BRANCH_NONE : jump_in_id; - // TODO: Remove? Can be replaced with stall. - assign force_nop_o = 1'b0; - - //////////////////////////////////////////////////////////////////////////////////////////// // Freeze Unit. This unit controls the pipeline stages // //////////////////////////////////////////////////////////////////////////////////////////// @@ -1286,6 +1272,7 @@ module controller assign reg_d_alu_is_reg_a_id = (regfile_alu_waddr_fw_i == instr_rdata_i[`REG_S1]) && (rega_used == 1'b1); assign reg_d_alu_is_reg_b_id = (regfile_alu_waddr_fw_i == instr_rdata_i[`REG_S2]) && (regb_used == 1'b1); //assign reg_d_alu_is_reg_c_id = (regfile_alu_waddr_fw_i == instr_rdata_i[`REG_RD]) && (regc_used == 1'b1); + assign reg_d_alu_is_reg_c_id = 1'b0; always_comb begin diff --git a/cs_registers.sv b/cs_registers.sv index e3ded6e8..3a56d506 100644 --- a/cs_registers.sv +++ b/cs_registers.sv @@ -51,17 +51,6 @@ module cs_registers input logic save_pc_id_i, // TODO: check if both IF/ID pc save is needed output logic [31:0] epcr_o, - // HWLoop Signals - input logic [`HWLOOP_REGS-1:0] [31:0] hwlp_start_addr_i, - input logic [`HWLOOP_REGS-1:0] [31:0] hwlp_end_addr_i, - input logic [`HWLOOP_REGS-1:0] [31:0] hwlp_counter_i, - - output logic [31:0] hwlp_start_o, - output logic [31:0] hwlp_end_o, - output logic [31:0] hwlp_counter_o, - output logic [1:0] hwlp_regid_o, - output logic [2:0] hwlp_we_o, - // Performance Counters input logic stall_id_i, // Stall ID stage @@ -125,7 +114,7 @@ module cs_registers // output mux always_comb begin - csr_rdata_o = 32'bx; + csr_rdata_o = 'x; if (is_constant == 1'b1) csr_rdata_o = constant_rdata_int; @@ -163,6 +152,8 @@ module cs_registers endcase end + assign register_rdata_int = csr[csr_index]; + // directly output some registers diff --git a/ex_stage.sv b/ex_stage.sv index 1e15e76a..086d4a33 100644 --- a/ex_stage.sv +++ b/ex_stage.sv @@ -53,7 +53,6 @@ module ex_stage input logic mult_en_i, input logic [1:0] mult_sel_subword_i, input logic [1:0] mult_signed_mode_i, - input logic mult_use_carry_i, input logic mult_mac_en_i, output logic [31:0] data_addr_ex_o, @@ -165,9 +164,6 @@ module ex_stage .operator_i ( alu_operator_i ), .operand_a_i ( alu_operand_a_i ), .operand_b_i ( alu_operand_b_i ), - .operand_c_i ( alu_operand_c_i ), - .carry_i ( 1'b0 ), - .flag_i ( 1'b0 ), .vector_mode_i ( vector_mode_i ), .cmp_mode_i ( alu_cmp_mode_i ), @@ -195,7 +191,6 @@ module ex_stage .vector_mode_i ( vector_mode_i ), .sel_subword_i ( mult_sel_subword_i ), .signed_mode_i ( mult_signed_mode_i ), - .use_carry_i ( mult_use_carry_i ), .mac_en_i ( mult_mac_en_i ), .op_a_i ( alu_operand_a_i ), diff --git a/id_stage.sv b/id_stage.sv index abe9873a..ed1e13a1 100644 --- a/id_stage.sv +++ b/id_stage.sv @@ -82,7 +82,6 @@ module id_stage output logic mult_en_ex_o, output logic [1:0] mult_sel_subword_ex_o, output logic [1:0] mult_signed_mode_ex_o, - output logic mult_use_carry_ex_o, output logic mult_mac_en_ex_o, output logic [4:0] regfile_waddr_ex_o, @@ -121,7 +120,6 @@ module id_stage output logic save_pc_if_o, output logic save_pc_id_o, output logic save_sr_o, - output logic restore_sr_o, // from hwloop regs input logic [`HWLOOP_REGS-1:0] [31:0] hwloop_start_addr_i, @@ -183,7 +181,6 @@ module id_stage logic exc_pc_sel; logic [2:0] pc_mux_sel_int; // selects next PC in if stage - logic force_nop_controller; logic force_nop_exc; logic irq_present; @@ -213,8 +210,6 @@ module id_stage logic [31:0] regfile_data_rb_id; logic [31:0] regfile_data_rc_id; - logic imm_sign_ext_sel; - // ALU Control logic [`ALU_OP_WIDTH-1:0] alu_operator; logic [1:0] alu_op_a_mux_sel; @@ -232,7 +227,6 @@ module id_stage logic mult_en; // multiplication is used instead of ALU logic [1:0] mult_sel_subword; // Select a subword when doing multiplications logic [1:0] mult_signed_mode; // Signed mode multiplication at the output of the controller, and before the pipe registers - logic mult_use_carry; // Enables carry in for the MAC logic mult_mac_en; // Enables the use of the accumulator // Register Write Control @@ -277,7 +271,7 @@ module id_stage - assign force_nop_o = force_nop_controller | force_nop_exc; + assign force_nop_o = force_nop_exc; assign pc_mux_sel_o = (exc_pc_sel == 1'b1) ? `PC_EXCEPTION : pc_mux_sel_int; @@ -542,8 +536,6 @@ module id_stage .fetch_enable_i ( fetch_enable_i ), .core_busy_o ( core_busy_o ), - .force_nop_o ( force_nop_controller ), - // Signal from-to PC pipe (instr rdata) and instr mem system (req and ack) .instr_rdata_i ( instr ), .instr_req_o ( instr_req_o ), @@ -553,7 +545,6 @@ module id_stage // Alu signals .alu_operator_o ( alu_operator ), - .extend_immediate_o ( imm_sign_ext_sel ), .alu_op_a_mux_sel_o ( alu_op_a_mux_sel ), .alu_op_b_mux_sel_o ( alu_op_b_mux_sel ), .alu_op_c_mux_sel_o ( alu_op_c_mux_sel ), @@ -567,7 +558,6 @@ module id_stage .mult_en_o ( mult_en ), .mult_sel_subword_o ( mult_sel_subword ), .mult_signed_mode_o ( mult_signed_mode ), - .mult_use_carry_o ( mult_use_carry ), .mult_mac_en_o ( mult_mac_en ), // Register file control signals @@ -617,9 +607,6 @@ module id_stage .dbg_set_npc_i ( dbg_set_npc_i ), .dbg_trap_o ( dbg_trap_o ), - // SPR Signals - .restore_sr_o ( restore_sr_o ), - // regfile port 1 .regfile_waddr_ex_i ( regfile_waddr_ex_o ), // Write address for register file from ex-wb- pipeline registers .regfile_we_ex_i ( regfile_we_ex_o ), @@ -773,7 +760,6 @@ module id_stage mult_en_ex_o <= 1'b0; mult_sel_subword_ex_o <= 2'b0; mult_signed_mode_ex_o <= 2'b0; - mult_use_carry_ex_o <= 1'b0; mult_mac_en_ex_o <= 1'b0; regfile_waddr_ex_o <= 5'b0; @@ -839,7 +825,6 @@ module id_stage mult_en_ex_o <= mult_en; mult_sel_subword_ex_o <= mult_sel_subword; mult_signed_mode_ex_o <= mult_signed_mode; - mult_use_carry_ex_o <= mult_use_carry; mult_mac_en_ex_o <= mult_mac_en; diff --git a/include/defines.sv b/include/defines.sv index 4d0d7edc..3a7f235e 100644 --- a/include/defines.sv +++ b/include/defines.sv @@ -196,7 +196,6 @@ endfunction // prettyPrintInstruction `define ALU_MOVHI 6'b001111 // Standard Operations `define ALU_ADD 6'b000_000 -`define ALU_ADDC 6'b000_001 `define ALU_SUB 6'b000_010 `define ALU_AND 6'b000_011 `define ALU_OR 6'b000_100 @@ -212,8 +211,6 @@ endfunction // prettyPrintInstruction // Set Lower Than Operations `define ALU_SLTS 6'b0011_00 `define ALU_SLTU 6'b0011_01 -// CMOV operation -`define ALU_CMOV 6'b0011_10 // Extension Operations `define ALU_EXTHS 6'b010_000 `define ALU_EXTWS 6'b010_001 diff --git a/mult.sv b/mult.sv index 1bb61585..5fd1b7a4 100644 --- a/mult.sv +++ b/mult.sv @@ -37,13 +37,11 @@ module mult input logic [1:0] vector_mode_i, input logic [1:0] sel_subword_i, input logic [1:0] signed_mode_i, - input logic use_carry_i, input logic mac_en_i, input logic [31:0] op_a_i, input logic [31:0] op_b_i, input logic [31:0] mac_i, - input logic carry_i, output logic [31:0] result_o, output logic carry_o, @@ -88,7 +86,7 @@ module mult case(vector_mode_i) default: // VEC_MODE32, VEC_MODE216 begin - result[32: 0] = mac_int + op_a_sel * op_b_sel + {32'b0, (use_carry_i & carry_i)}; + result[32: 0] = mac_int + op_a_sel * op_b_sel; end `VEC_MODE16: diff --git a/riscv_core.sv b/riscv_core.sv index 6a9d7e7b..fcb4dafb 100644 --- a/riscv_core.sv +++ b/riscv_core.sv @@ -130,7 +130,6 @@ module riscv_core logic mult_en_ex; logic [1:0] mult_sel_subword_ex; logic [1:0] mult_signed_mode_ex; - logic mult_use_carry_ex; logic mult_mac_en_ex; // Register Write Control @@ -179,8 +178,6 @@ module riscv_core logic [31:0] epcr; logic save_pc_if; logic save_pc_id; - logic save_sr; - logic restore_sr; // hwloop data from ALU logic [31:0] hwlp_cnt_ex; // from id to ex stage (hwloop_regs) @@ -362,7 +359,6 @@ module riscv_core .mult_en_ex_o ( mult_en_ex ), // from ID to EX stage .mult_sel_subword_ex_o ( mult_sel_subword_ex ), // from ID to EX stage .mult_signed_mode_ex_o ( mult_signed_mode_ex ), // from ID to EX stage - .mult_use_carry_ex_o ( mult_use_carry_ex ), // from ID to EX stage .mult_mac_en_ex_o ( mult_mac_en_ex ), // from ID to EX stage .regfile_waddr_ex_o ( regfile_waddr_ex ), @@ -401,8 +397,6 @@ module riscv_core .irq_enable_i ( irq_enable ), // global interrupt enable .save_pc_if_o ( save_pc_if ), // control signal to save pc .save_pc_id_o ( save_pc_id ), // control signal to save pc - .save_sr_o ( save_sr ), // control signal to save status register - .restore_sr_o ( restore_sr ), // restore status register // from hwloop regs .hwloop_start_addr_i ( hwlp_start_addr ), @@ -470,7 +464,6 @@ module riscv_core .mult_en_i ( mult_en_ex ), .mult_sel_subword_i ( mult_sel_subword_ex ), .mult_signed_mode_i ( mult_signed_mode_ex ), - .mult_use_carry_i ( mult_use_carry_ex ), .mult_mac_en_i ( mult_mac_en_ex ), // interface with CSRs @@ -613,17 +606,6 @@ module riscv_core .csr_op_i ( csr_op ), .csr_rdata_o ( csr_rdata ), - // HWLoop signals - .hwlp_start_addr_i ( hwlp_start_addr ), - .hwlp_end_addr_i ( hwlp_end_addr ), - .hwlp_counter_i ( hwlp_counter ), - - .hwlp_start_o ( sp_hwlp_start ), - .hwlp_end_o ( sp_hwlp_end ), - .hwlp_counter_o ( sp_hwlp_cnt ), - .hwlp_regid_o ( sp_hwlp_regid ), - .hwlp_we_o ( sp_hwlp_we ), - .curr_pc_if_i ( current_pc_if ), // from IF stage .curr_pc_id_i ( current_pc_id ), // from IF stage .save_pc_if_i ( save_pc_if ), @@ -654,58 +636,6 @@ module riscv_core assign dbg_rdata = (dbg_sp_mux == 1'b0) ? dbg_reg_rdata : csr_rdata; - /* - sp_registers sp_registers_i - ( - .clk ( clk ), - .rst_n ( rst_n ), - - // Core and Cluster ID from outside - .core_id_i ( core_id_i ), - .cluster_id_i ( cluster_id_i ), - - // Interface to Special register (SRAM LIKE) - .sp_addr_i ( sp_addr ), - .sp_wdata_i ( sp_wdata ), - .sp_op_i ( sp_op ), - .sp_rdata_o ( sp_rdata ), - - // Stall direct write - .enable_direct_write_i ( stall_wb ), - - // HWLoop signals - .hwlp_start_addr_i ( hwlp_start_addr ), - .hwlp_end_addr_i ( hwlp_end_addr ), - .hwlp_counter_i ( hwlp_counter ), - - .hwlp_start_o ( sp_hwlp_start ), - .hwlp_end_o ( sp_hwlp_end ), - .hwlp_counter_o ( sp_hwlp_cnt ), - .hwlp_regid_o ( sp_hwlp_regid ), - .hwlp_we_o ( sp_hwlp_we ), - - .curr_pc_if_i ( current_pc_if ), // from IF stage - .curr_pc_id_i ( current_pc_id ), // from IF stage - .save_pc_if_i ( save_pc_if ), - .save_pc_id_i ( save_pc_id ), - .save_sr_i ( save_sr ), - .restore_sr_i ( restore_sr ), - .epcr_o ( epcr ), - .irq_enable_o ( irq_enable ), - - .npc_o ( dbg_npc ), // PC from debug unit - .set_npc_o ( dbg_set_npc ) // set PC to new value - ); - - // Mux for SPR access through Debug Unit - assign sp_addr = (dbg_sp_mux == 1'b0) ? sp_addr_wb : dbg_reg_addr; - assign sp_wdata = (dbg_sp_mux == 1'b0) ? regfile_rb_data_wb : dbg_reg_wdata; - assign sp_op = (dbg_sp_mux == 1'b0) ? sp_op_wb - : (dbg_reg_we == 1'b1 ? `CSR_OP_WRITE : `CSR_OP_NONE); - assign dbg_rdata = (dbg_sp_mux == 1'b0) ? dbg_reg_rdata : sp_rdata; - */ - - /* //////////////////////////////////////////////