diff --git a/alu.sv b/alu.sv index fca40f0b..2cf04b64 100644 --- a/alu.sv +++ b/alu.sv @@ -15,6 +15,7 @@ // Igor Loi - igor.loi@unibo.it // // Andreas Traber - atraber@student.ethz.ch // // // +// Design Name: ALU // // Project Name: RI5CY // // Language: SystemVerilog // // // diff --git a/compressed_decoder.sv b/compressed_decoder.sv index 8ddb39ca..725ac4c4 100644 --- a/compressed_decoder.sv +++ b/compressed_decoder.sv @@ -11,9 +11,6 @@ //////////////////////////////////////////////////////////////////////////////// // Engineer: Sven Stucki - svstucki@student.ethz.ch // // // -// Additional contributions by: // -// // -// // // Design Name: Compressed instruction decoder // // Project Name: RI5CY // // Language: SystemVerilog // diff --git a/controller.sv b/controller.sv index ae212589..4564e89f 100644 --- a/controller.sv +++ b/controller.sv @@ -1,6 +1,14 @@ +// Copyright 2015 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the “License”); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + //////////////////////////////////////////////////////////////////////////////// -// Company: IIS @ ETHZ - Federal Institute of Technology // -// // // Engineer: Matthias Baer - baermatt@student.ethz.ch // // // // Additional contributions by: // @@ -8,26 +16,12 @@ // Andreas Traber - atraber@student.ethz.ch // // Sven Stucki - svstucki@student.ethz.ch // // // -// // -// Create Date: 19/09/2013 // -// Design Name: RISC-V processor core // -// Module Name: controller.sv // +// Design Name: Main controller // // Project Name: RI5CY // // Language: SystemVerilog // // // // Description: Main CPU controller of the processor // // // -// // -// Revision: // -// Revision v0.1 - File Created // -// Revision v0.2 - (August 8th 2014) Changed port and signal names, added // -// comments // -// Revision v0.3 - (December 1th 2014) Merged debug unit // -// Revision v0.4 - (January 6th 2015) Added vectorial instructions // -// Revision v0.5 - (Sept 15th 2015) Separated controller and decoder // -// // -// // -// // //////////////////////////////////////////////////////////////////////////////// `include "riscv_defines.sv" diff --git a/cs_registers.sv b/cs_registers.sv index 19f80830..e4a0a17c 100644 --- a/cs_registers.sv +++ b/cs_registers.sv @@ -12,8 +12,9 @@ // Engineer: Sven Stucki - svstucki@student.ethz.ch // // // // Additional contributions by: // +// Andreas Traber - atraber@iis.ee.ethz.ch // // // -// // +// Design Name: Control and Status Registers // // Project Name: RI5CY // // Language: SystemVerilog // // // diff --git a/debug_unit.sv b/debug_unit.sv index 86b3e857..96343bbb 100644 --- a/debug_unit.sv +++ b/debug_unit.sv @@ -15,7 +15,7 @@ // Andreas Traber - atraber@student.ethz.ch // // Sven Stucki - svstucki@student.ethz.ch // // // -// // +// Design Name: Debug Unit // // Project Name: RI5CY // // Language: SystemVerilog // // // diff --git a/decoder.sv b/decoder.sv index 862f4549..39b774b5 100644 --- a/decoder.sv +++ b/decoder.sv @@ -16,7 +16,7 @@ // Igor Loi - igor.loi@unibo.it // // Sven Stucki - svstucki@student.ethz.ch // // // -// // +// Design Name: Decoder // // Project Name: RI5CY // // Language: SystemVerilog // // // diff --git a/ex_stage.sv b/ex_stage.sv index f56f4006..fe4e5230 100644 --- a/ex_stage.sv +++ b/ex_stage.sv @@ -15,7 +15,6 @@ // Igor Loi - igor.loi@unibo.it // // Sven Stucki - svstucki@student.ethz.ch // // // -// // // Design Name: Excecute stage // // Project Name: RI5CY // // Language: SystemVerilog // diff --git a/exc_controller.sv b/exc_controller.sv index 45a80f09..02954ac2 100644 --- a/exc_controller.sv +++ b/exc_controller.sv @@ -14,7 +14,7 @@ // Additional contributions by: // // Sven Stucki - svstucki@student.ethz.ch // // // -// // +// Design Name: Exception Controller // // Project Name: RI5CY // // Language: SystemVerilog // // // diff --git a/hwloop_controller.sv b/hwloop_controller.sv index 05fb34f7..ee9194f8 100644 --- a/hwloop_controller.sv +++ b/hwloop_controller.sv @@ -11,9 +11,6 @@ //////////////////////////////////////////////////////////////////////////////// // Engineer: Michael Gautschi - gautschi@iis.ee.ethz.ch // // // -// Additional contributions by: // -// // -// // // Design Name: hwloop controller // // Project Name: RI5CY // // Language: SystemVerilog // diff --git a/hwloop_regs.sv b/hwloop_regs.sv index 0292ed26..62d35b09 100644 --- a/hwloop_regs.sv +++ b/hwloop_regs.sv @@ -11,9 +11,6 @@ //////////////////////////////////////////////////////////////////////////////// // Engineer: Michael Gautschi - gautschi@iis.ee.ethz.ch // // // -// Additional contributions by: // -// // -// // // Design Name: hwloop regs // // Project Name: RI5CY // // Language: SystemVerilog // diff --git a/id_stage.sv b/id_stage.sv index 122285eb..12930819 100644 --- a/id_stage.sv +++ b/id_stage.sv @@ -16,8 +16,7 @@ // Andreas Traber - atraber@student.ethz.ch // // Sven Stucki - svstucki@student.ethz.ch // // // -// // -// Design Name: Decode stage // +// Design Name: Instruction Decode Stage // // Project Name: RI5CY // // Language: SystemVerilog // // // diff --git a/if_stage.sv b/if_stage.sv index 84aa98f7..a0ad9a83 100644 --- a/if_stage.sv +++ b/if_stage.sv @@ -16,8 +16,7 @@ // Andreas Traber - atraber@student.ethz.ch // // Sven Stucki - svstucki@student.ethz.ch // // // -// // -// Design Name: RISC-V processor core // +// Design Name: Instruction Fetch Stage // // Project Name: RI5CY // // Language: SystemVerilog // // // diff --git a/load_store_unit.sv b/load_store_unit.sv index 98251793..779e176f 100644 --- a/load_store_unit.sv +++ b/load_store_unit.sv @@ -14,7 +14,6 @@ // Additional contributions by: // // Andreas Traber - atraber@iis.ee.ethz.ch // // // -// // // Design Name: Load Store Unit // // Project Name: RI5CY // // Language: SystemVerilog // diff --git a/mult.sv b/mult.sv index d5139e7e..35259105 100644 --- a/mult.sv +++ b/mult.sv @@ -14,8 +14,7 @@ // Additional contributions by: // // Andreas Traber - atraber@student.ethz.ch // // // -// // -// Design Name: Vectorial Multiplier and MAC // +// Design Name: Subword multiplier and MAC // // Project Name: RI5CY // // Language: SystemVerilog // // // diff --git a/prefetch_L0_buffer.sv b/prefetch_L0_buffer.sv index 692ce2da..82a35853 100644 --- a/prefetch_L0_buffer.sv +++ b/prefetch_L0_buffer.sv @@ -9,12 +9,12 @@ // specific language governing permissions and limitations under the License. //////////////////////////////////////////////////////////////////////////////// -// Engineer: Andreas Traber - atraber@iis.ee.ethz.ch // +// Engineer: Igor Loi - igor.loi@unibo.it // // // // Additional contributions by: // +// Andreas Traber - atraber@iis.ee.ethz.ch // // // -// // -// Design Name: RISC-V processor core // +// Design Name: Prefetcher Buffer for 128 bit memory interface // // Project Name: RI5CY // // Language: SystemVerilog // // // diff --git a/prefetch_buffer.sv b/prefetch_buffer.sv index 05018bff..cc68aa04 100644 --- a/prefetch_buffer.sv +++ b/prefetch_buffer.sv @@ -11,10 +11,7 @@ //////////////////////////////////////////////////////////////////////////////// // Engineer: Andreas Traber - atraber@iis.ee.ethz.ch // // // -// Additional contributions by: // -// // -// // -// Design Name: RISC-V processor core // +// Design Name: Prefetcher Buffer for 32 bit memory interface // // Project Name: RI5CY // // Language: SystemVerilog // // // diff --git a/register_file.sv b/register_file.sv index f5ef57e5..d7709c20 100644 --- a/register_file.sv +++ b/register_file.sv @@ -8,6 +8,22 @@ // CONDITIONS OF ANY KIND, either express or implied. See the License for the // specific language governing permissions and limitations under the License. +//////////////////////////////////////////////////////////////////////////////// +// Engineer: Antonio Pullini - pullinia@iis.ee.ethz.ch // +// // +// Additional contributions by: // +// Sven Stucki - svstucki@student.ethz.ch // +// // +// Design Name: RISC-V register file // +// Project Name: RI5CY // +// Language: SystemVerilog // +// // +// Description: Register file with 31x 32 bit wide registers. Register 0 // +// is fixed to 0. This register file is based on latches and // +// is thus smaller than the flip-flop based register file. // +// // +//////////////////////////////////////////////////////////////////////////////// + module riscv_register_file #( parameter ADDR_WIDTH = 5, diff --git a/register_file_ff.sv b/register_file_ff.sv index 7277116f..e94c06a3 100644 --- a/register_file_ff.sv +++ b/register_file_ff.sv @@ -8,18 +8,17 @@ // CONDITIONS OF ANY KIND, either express or implied. See the License for the // specific language governing permissions and limitations under the License. -/****************************************************************************** - * * - * ERC Multitherman Lab @ DEI - University of Bologna * - * Viale Pepoli 3/2 - 40136 * - * Bologna - phone 0512092759 * - * * - * Engineer: Francesco Conti - f.conti@unibo.it * - * * - * Project: PULP FPGA emulator * - * Description: Triple-port behavioral register file * - * * - ******************************************************************************/ +//////////////////////////////////////////////////////////////////////////////// +// Engineer: Francesco Conti - f.conti@unibo.it // +// // +// Design Name: RISC-V register file // +// Project Name: RI5CY // +// Language: SystemVerilog // +// // +// Description: Register file with 31x 32 bit wide registers. Register 0 // +// is fixed to 0. This register file is based on flip-flops. // +// // +//////////////////////////////////////////////////////////////////////////////// module riscv_register_file #( diff --git a/riscv_core.sv b/riscv_core.sv index 4bdf9685..bee486fd 100644 --- a/riscv_core.sv +++ b/riscv_core.sv @@ -8,6 +8,23 @@ // CONDITIONS OF ANY KIND, either express or implied. See the License for the // specific language governing permissions and limitations under the License. +//////////////////////////////////////////////////////////////////////////////// +// Engineer: Matthias Baer - baermatt@student.ethz.ch // +// // +// Additional contributions by: // +// Igor Loi - igor.loi@unibo.it // +// Andreas Traber - atraber@student.ethz.ch // +// Sven Stucki - svstucki@student.ethz.ch // +// // +// Design Name: Top level module // +// Project Name: RI5CY // +// Language: SystemVerilog // +// // +// Description: Top level module of the RISC-V core. // +// // +//////////////////////////////////////////////////////////////////////////////// + + `include "riscv_defines.sv" module riscv_core