From d8b97370398d79f1e1d16bf8af32ba8e54873cb4 Mon Sep 17 00:00:00 2001 From: udinator Date: Fri, 28 Feb 2020 17:02:07 -0800 Subject: [PATCH] update riscv_core_setting (#633) Signed-off-by: Udi --- dv/uvm/core_ibex/riscv_dv_extension/riscv_core_setting.sv | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/dv/uvm/core_ibex/riscv_dv_extension/riscv_core_setting.sv b/dv/uvm/core_ibex/riscv_dv_extension/riscv_core_setting.sv index e5b85e5e..2b751a9b 100644 --- a/dv/uvm/core_ibex/riscv_dv_extension/riscv_core_setting.sv +++ b/dv/uvm/core_ibex/riscv_dv_extension/riscv_core_setting.sv @@ -26,6 +26,9 @@ parameter int VLEN = 512; parameter int ELEN = 64; parameter int SLEN = 64; +// Number of harts +parameter int NUM_HARTS = 1; + // Parameter for SATP mode, set to BARE if address translation is not supported parameter satp_mode_t SATP_MODE = BARE; @@ -67,7 +70,7 @@ bit support_sfence = 0; //----------------------------------------------------------------------------- // Number of kernel data pages -int num_of_kernel_data_pages = 2; +int num_of_kernel_data_pages = 0; // Byte size of kernel data pages int kernel_data_page_size = 4096;