diff --git a/alu.sv b/alu.sv index 6ac968bf..51e7a138 100644 --- a/alu.sv +++ b/alu.sv @@ -617,7 +617,7 @@ module alu end // Set Lower Than Operations (result = 1, if a < b) - `ALU_SLTS, `ALU_SLTU: result_o = {30'b0, cmp_result[0]}; + `ALU_SLTS, `ALU_SLTU: result_o = {31'b0, cmp_result[0]}; `ALU_FF1: result_o = {26'h0, ff1_result}; `ALU_FL1: result_o = {26'h0, fl1_result}; diff --git a/compressed_decoder.sv b/compressed_decoder.sv index 5658fd27..cb56e9f4 100644 --- a/compressed_decoder.sv +++ b/compressed_decoder.sv @@ -151,13 +151,13 @@ module compressed_decoder 3'b100: begin unique case (instr_i[6:5]) // c.addin -> addi rd', rs1', imm - 2'b00: instr_o = {{8 {instr_i[12]}}, instr_i[12:10], 2'b01, instr_i[9:7], 3'b000, 2'b01, instr_i[4:2], `OPCODE_OPIMM}; + 2'b00: instr_o = {{9 {instr_i[12]}}, instr_i[12:10], 2'b01, instr_i[9:7], 3'b000, 2'b01, instr_i[4:2], `OPCODE_OPIMM}; // c.xorin -> xori rd', rs1', imm - 2'b01: instr_o = {{8 {instr_i[12]}}, instr_i[12:10], 2'b01, instr_i[9:7], 3'b100, 2'b01, instr_i[4:2], `OPCODE_OPIMM}; + 2'b01: instr_o = {{9 {instr_i[12]}}, instr_i[12:10], 2'b01, instr_i[9:7], 3'b100, 2'b01, instr_i[4:2], `OPCODE_OPIMM}; // c.orin -> ori rd', rs1', imm - 2'b10: instr_o = {{8 {instr_i[12]}}, instr_i[12:10], 2'b01, instr_i[9:7], 3'b110, 2'b01, instr_i[4:2], `OPCODE_OPIMM}; + 2'b10: instr_o = {{9 {instr_i[12]}}, instr_i[12:10], 2'b01, instr_i[9:7], 3'b110, 2'b01, instr_i[4:2], `OPCODE_OPIMM}; // c.andin -> andi rd', rs1', imm - 2'b11: instr_o = {{8 {instr_i[12]}}, instr_i[12:10], 2'b01, instr_i[9:7], 3'b111, 2'b01, instr_i[4:2], `OPCODE_OPIMM}; + 2'b11: instr_o = {{9 {instr_i[12]}}, instr_i[12:10], 2'b01, instr_i[9:7], 3'b111, 2'b01, instr_i[4:2], `OPCODE_OPIMM}; default: illegal_instr_o = 1'b1; endcase if (instr_i[12:10] == 3'b0) illegal_instr_o = 1'b1; diff --git a/controller.sv b/controller.sv index c9f56d73..a28b87bd 100644 --- a/controller.sv +++ b/controller.sv @@ -56,7 +56,7 @@ module controller output logic [1:0] alu_op_b_mux_sel_o, // Operator b is selected between reg value or immediate output logic alu_op_c_mux_sel_o, // Operator c is selected between reg value or PC output logic alu_pc_mux_sel_o, // selects IF or ID PC for ALU computations - output logic [3:0] immediate_mux_sel_o, + output logic [2:0] immediate_mux_sel_o, output logic [1:0] vector_mode_o, // selects between 32 bit, 16 bit and 8 bit vectorial modes output logic scalar_replication_o, // activates scalar_replication for vectorial mode @@ -1273,7 +1273,7 @@ module controller case (dbg_fsm_cs) DBG_IDLE: begin - if(trap_hit_i == 1'b1 && stall_ex_o == 1'b0 && jump_in_id_o == 1'b0) + if(trap_hit_i == 1'b1 && stall_ex_o == 1'b0 && jump_in_id_o == 2'b0) begin dbg_halt = 1'b1; dbg_fsm_ns = DBG_EX; diff --git a/id_stage.sv b/id_stage.sv index f4b55756..c1076e88 100644 --- a/id_stage.sv +++ b/id_stage.sv @@ -224,7 +224,7 @@ module id_stage logic [1:0] alu_vec_ext; logic alu_pc_mux_sel; - logic [3:0] immediate_mux_sel; + logic [2:0] immediate_mux_sel; // Multiplier Control logic mult_en; // multiplication is used instead of ALU @@ -293,10 +293,10 @@ module id_stage // immediate extraction and sign extension assign imm_i_type = { {20 {instr[31]}}, instr[31:20] }; assign imm_s_type = { {20 {instr[31]}}, instr[31:25], instr[11:7] }; - assign imm_sb_type = { {20 {instr[31]}}, instr[31], instr[7], + assign imm_sb_type = { {19 {instr[31]}}, instr[31], instr[7], instr[30:25], instr[11:8], 1'b0 }; assign imm_u_type = { instr[31:12], {12 {1'b0}} }; - assign imm_uj_type = { {20 {instr[31]}}, instr[19:12], + assign imm_uj_type = { {12 {instr[31]}}, instr[19:12], instr[20], instr[30:21], 1'b0 }; // immediate for CSR manipulatin (zero extended) @@ -311,7 +311,7 @@ module id_stage assign regfile_waddr_id = instr[`REG_D]; //assign alu_vec_ext = instr[9:8]; TODO - assign alu_vec_ext = 1'b0; + assign alu_vec_ext = '0; // Second Register Write Adress Selection @@ -778,7 +778,7 @@ module id_stage regfile_wdata_mux_sel_ex_o <= 1'b0; regfile_we_ex_o <= 1'b0; - regfile_alu_waddr_ex_o <= 4'b0; + regfile_alu_waddr_ex_o <= 5'b0; regfile_alu_we_ex_o <= 1'b0; prepost_useincr_ex_o <= 1'b0; diff --git a/include/defines.sv b/include/defines.sv index 44ece07d..e8036909 100644 --- a/include/defines.sv +++ b/include/defines.sv @@ -330,10 +330,10 @@ endfunction // prettyPrintInstruction `define OP_C_JT 1'b1 // operand b immediate selection -`define IMM_I 2'b00 -`define IMM_S 2'b01 -`define IMM_U 2'b10 -`define IMM_PCINCR 2'b11 +`define IMM_I 3'b000 +`define IMM_S 3'b001 +`define IMM_U 3'b010 +`define IMM_PCINCR 3'b011 // PC mux selector defines `define PC_INCR 3'b000 diff --git a/mult.sv b/mult.sv index 774a6216..e4b25cab 100644 --- a/mult.sv +++ b/mult.sv @@ -61,7 +61,7 @@ module mult logic [32:0] mac_int; - assign mac_int = (mac_en_i == 1'b1) ? mac_i : 33'b0; + assign mac_int = (mac_en_i == 1'b1) ? {1'b0, mac_i} : 33'b0; // this block performs the subword selection and sign extensions always_comb @@ -92,7 +92,7 @@ module mult case(vector_mode_i) default: // VEC_MODE32, VEC_MODE216 begin - result[32: 0] = mac_int + op_a_sel * op_b_sel + (use_carry_i & carry_i); + result[32: 0] = mac_int + op_a_sel * op_b_sel + {32'b0, (use_carry_i & carry_i)}; end `VEC_MODE16: diff --git a/riscv_core.sv b/riscv_core.sv index a8fa951d..772b2e4d 100644 --- a/riscv_core.sv +++ b/riscv_core.sv @@ -806,7 +806,7 @@ module riscv_core logic [31:0] instr; logic compressed; logic [31:0] pc; - logic [5:0] rd, rs1, rs2; + logic [4:0] rd, rs1, rs2; logic [31:0] rs1_value, rs2_value; logic [31:0] imm; string mnemonic;