diff --git a/docs/datasheet/content/debug.tex b/docs/datasheet/content/debug.tex
index 3d1cc7b7..ca6d7d5d 100644
--- a/docs/datasheet/content/debug.tex
+++ b/docs/datasheet/content/debug.tex
@@ -1,2 +1,89 @@
 \chapter{Debug}
 \label{chap:debug}
+
+\rvcore has full support for software breakpoints (\instr{ebreak}), access to
+general-purpose and control and status registers via a debug port. It is also
+possible to halt the core from the debug port and put it into single-stepping
+mode. Similarly when an interrupt occurs, instead of jumping to the interrupt
+handler the core can trap to an attached debugger.
+
+The debug port uses the following interface:
+
+\begin{table}[H]
+ \caption{Debug Signals}
+ \label{tab:debug_signals}
+  \begin{tabularx}{\textwidth}{@{}llX@{}} \toprule
+    \textbf{Signal}                 & \textbf{Direction} & \textbf{Description} \\ \toprule
+    \signal{dbginf\_strobe\_i}      & \textbf{input}     & Command request \\ \hline
+    \signal{dbginf\_we\_i}          & \textbf{input}     & Write Enable \\ \hline
+    \signal{dbginf\_addr\_i[15:0]}  & \textbf{input}     & Address \\ \hline
+    \signal{dbginf\_data\_i[31:0]}  & \textbf{input}     & Input data \\ \hline
+    \signal{dbginf\_data\_o}        & \textbf{output}    & Output data \\ \hline
+    \signal{dbginf\_ack\_o}         & \textbf{output}    & Command was executed \\ \hline
+    \signal{dbginf\_stall\_i}       & \textbf{input}     & Stall the core \\ \hline
+    \signal{dbginf\_bp\_o}          & \textbf{output}    & Breakpoint hit \\ \bottomrule
+  \end{tabularx}
+\end{table}
+
+This interface is natively supported by the advanced debug bridge that is used
+by \pulp and \pulpino, see also the documentation of this bridge.
+
+
+\section{Debug Address Map}
+
+This debug address map is not optimal and should be changed!
+See the OpenSoC debug project for a proposal for a better address map.
+
+\begin{table}[H]
+ \caption{Control and Status Register Map}
+ \label{tab:debug_map}
+ \centering\begin{tabularx}{\linewidth}{@{}|cc|c|l|X|@{}} \toprule
+   \multicolumn{2}{|c|}{\textbf{Dbginf Addr [15:0]}} & \textbf{Hex} & \textbf{Name} & \textbf{Description} \\ \hline
+   Grp [15:11] & Addr [10:0] & & & \\ \toprule
+   \texttt{0\_0001} & \texttt{000\_000X\_XXXX} & \texttt{0x0800 - 0x081F} & GPR   & General-Purpose Registers \\ \hline
+   \texttt{0\_0110} & \texttt{000\_0000\_0000} & \texttt{0x3000 - 0x3014} & Debug & Debug Registers \\ \hline
+   \texttt{?\_????} & \texttt{XXX\_XXXX\_XXXX} & \texttt{               } & CSR   & Everything else is mapped to CSR \\ \bottomrule
+  \end{tabularx}
+\end{table}
+
+
+\subsection{Debug Register: DMR1}
+
+\textbf{CSR Address:} \texttt{0x3010} \\
+\textbf{Reset Value:} \texttt{0x0000\_0000} \\
+\begin{figure}[H]
+  \centering
+  \begin{bytefield}[endianness=big,bitheight=60pt]{32}
+    \bitheader{31,23,22,0} \\
+    \bitbox{9}{ Unused }
+    \bitbox{1}{\rotatebox{90}{\tiny Single-Stepping    }}
+    \bitbox{22}{ Unused }
+  \end{bytefield}
+  \caption{DMR1}
+\end{figure}
+
+Single-stepping activates single-stepping mode, meaning the core traps to the
+debugger after one instruction has been executed.
+
+\subsection{Debug Register: DSR}
+
+\textbf{CSR Address:} \texttt{0x3014} \\
+\textbf{Reset Value:} \texttt{0x0000\_0000} \\
+\begin{figure}[H]
+  \centering
+  \begin{bytefield}[endianness=big,bitheight=60pt]{32}
+    \bitheader{31,8,7,6,0} \\
+    \bitbox{24}{ Unused }
+    \bitbox{1}{\rotatebox{90}{\tiny INTE   }}
+    \bitbox{1}{\rotatebox{90}{\tiny IIE    }}
+    \bitbox{6}{ Unused }
+  \end{bytefield}
+  \caption{DMR1}
+\end{figure}
+
+\signal{IIE} stands for illegal instruction exception enabled. A value of
+\signal{1} means trap to the debugger when an illegal instruction is
+encountered.
+
+\signal{INTE} stands for interrupt enabled. A value of \signal{1} means trap to
+the debugger when an interrupt is encountered.
diff --git a/docs/datasheet/content/exceptions.tex b/docs/datasheet/content/exceptions.tex
index c3e6eca6..67eca5ca 100644
--- a/docs/datasheet/content/exceptions.tex
+++ b/docs/datasheet/content/exceptions.tex
@@ -1,4 +1,53 @@
 \chapter{Exceptions and Interrupts}
 \label{chap:exceptions}
 
-\rvcore supports 
+\rvcore supports vectorized interrupts, exceptions on illegal instructions and
+exceptions on load and store instructions to invalid addresses.
+
+
+\begin{table}[H]
+ \caption{Interrupt/exception offset vector table}
+ \label{tab:exc_table}
+ \centering\begin{tabular}{@{}ll@{}} \toprule
+    \textbf{Address} & \textbf{Description} \\ \toprule
+    \signal{0x00} - \signal{0x0000\_007C} & Interrupts 0 - 31 \\ \hline
+    \signal{0x80} & Reset \\ \hline
+    \signal{0x84} & Illegal Instruction \\ \hline
+    \signal{0x88} & \instr{ECALL} instruction executed \\ \hline
+    \signal{0x8C} & LSU error (invalid memory access) \\ \bottomrule
+  \end{tabular}
+\end{table}
+
+The instruction addresses in Table~\ref{tab:exc_table} are considered as an
+offset to the boot address given to the core. Specifically the core jumps to
+address \signal{$\{$boot\_addr[31:8], offset[7:0]$\}$} when encountering an
+exception/interrupt.
+
+
+\section{Interrupts}
+\rvcore uses vectorized interrupts, specifically it provides 32 separate
+interrupt lines. Interrupts can only be enabled/disabled on a global basis and
+not individually. It is assumed that there is an event/interrupt controller
+outside of the core that performs masking and buffering of the interrupt lines.
+The global interrupt enable is done via the CSR register \signal{mstatus}.
+
+\section{Exceptions}
+
+The illegal instruction exception, the load and store invalid memory access
+exceptions and ecall instruction exceptions can not be disabled and are always
+active.
+
+The illegal instruction exception and the load and store invalid memory access
+exceptions are precise exceptions, i.e. the value of \signal{mepc} will be the
+instruction address that caused it.
+
+\section{Handling}
+
+\rvcore does not support nested interrupt/exception handling. Exceptions inside
+interrupt/exception handlers are ignored and thus a user must ensure that such
+a situation does not happen, as otherwise the behaviour is undefined.
+
+Upon executing an \instr{eret} instruction, the core jumps to the program
+counter saved in the CSR register \signal{mepc}. When entering an
+interrupt/exception handler, the core sets \signal{mepc} to the current program
+counter.
diff --git a/docs/datasheet/content/perfcounters.tex b/docs/datasheet/content/perfcounters.tex
index 858b71cc..1681a308 100644
--- a/docs/datasheet/content/perfcounters.tex
+++ b/docs/datasheet/content/perfcounters.tex
@@ -1,27 +1,15 @@
 \chapter{Performance Counters}
 \label{chap:perf_count}
 
-Performance Counters in \orion are placed inside the Special-Purpose Registers
-and can be accessed with \instr{l.mfspr} and \instr{l.mtspr}.
-Figure~\ref{fig:spr_addr} shows the SPR address format and
-Table~\ref{tab:pc_spr_addr} shows the respective addresses for configuration and
-access to the performance counters.
-
-\begin{table}[H]
- \caption{PC SPR Addresses}
- \label{tab:pc_spr_addr}
- \centering\begin{tabularx}{\textwidth}{@{}ccccX@{}} \toprule
-   \textbf{Group \#} & \textbf{Reg \#} & Reg Name     & Access  & Description\\ \toprule
-                   7 &  0 - 31         & PCCR0-PCCR31 & R/W     & Performance Counters Count Registers \\ \hline
-                   7 &  32             & PCER         & R/W     & Performance Counters Event Register \\ \hline
-                   7 &  33             & PCMR         & R/W     & Performance Counters Mode Register \\ \bottomrule
-  \end{tabularx}
-\end{table}
+Performance Counters in \rvcore are placed inside the Control and Status
+Registers and can be accessed with \instr{csrr} and \instr{csrw} instructions.
+See Table~\ref{tab:csr_map} for the address map of the performance counter
+registers.
 
 
 \section{Performance Counter Mode Register (PCMR)}
 
-\csrDesc{0x3821}{0x0000\_0003}{PCMR}{
+\csrDesc{0x7A1}{0x0000\_0003}{PCMR}{
   \begin{bytefield}[endianness=big,bitheight=60pt]{32}
     \bitheader{31,1,0} \\
     \bitbox{30}{ Unused                            }
@@ -30,17 +18,17 @@ access to the performance counters.
   \end{bytefield}
 }
 
-The \instr{Global Enable} bit controls all performance counters, i.e. if it is set
-to \instr{0}, all performance counters are deactivated.
-After reset, the \instr{Global Enable} bit is set.
+The \instr{Global Enable} bit controls all performance counters, i.e. if it is
+set to \instr{0}, all performance counters are deactivated. After reset, the
+\instr{Global Enable} bit is set.
 
 The \instr{Saturation} bit controls saturation behaviour of the performance
-counters. If it is set, saturating arithmetic is used.
-After reset, the \instr{Saturation} bit is set.
+counters. If it is set, saturating arithmetic is used. After reset, the
+\instr{Saturation} bit is set.
 
 \section{Performance Counter Event Register (PCER)}
 
-\csrDesc{0x3820}{0x0000\_0000}{PCER}{
+\csrDesc{0x7A0}{0x0000\_0000}{PCER}{
   \begin{bytefield}[endianness=big,bitheight=60pt]{32}
     \bitheader{31,16,15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0} \\
     \bitbox{1}{\rotatebox{90}{\tiny (ALL)                 }}
@@ -80,7 +68,7 @@ accesses separately.
 
 \section{Performance Counter Counter Registers (PCCR0-31)}
 
-\csrDesc{0x3800 - 0x381F}{0x0000\_0000}{PCCR0-31}{
+\csrDesc{0x780 - 0x79F}{0x0000\_0000}{PCCR0-31}{
   \begin{bytefield}[endianness=big]{32}
     \bitheader{31,0} \\
     \bitbox{32}{Unsigned integer counter value}
@@ -104,11 +92,11 @@ controlled by the \instr{saturation} bit in PCMR.
   \textbf{PCCR8}  & \textbf{BRANCH}       & Number of branches, counts taken and not taken branches\\ \hline
   \textbf{PCCR9}  & \textbf{BTAKEN}       & Number of taken branches \\ \hline
   \textbf{PCCR10} & \textbf{RVC}          & Number of compressed instructions executed \\ \hline
-  \textbf{PCCR11} & \textbf{LD\_EXT}      & Number of memory loads to EXT executed. Misaligned accesses are counted twice. Every non-TCDM access is considered external \\ \hline
-  \textbf{PCCR12} & \textbf{ST\_EXT}      & Number of memory stores to EXT executed. Misaligned accesses are counted twice. Every non-TCDM access is considered external \\ \hline
-  \textbf{PCCR13} & \textbf{LD\_EXT\_CYC} & Cycles used for memory loads to EXT. Every non-TCDM access is considered external \\ \hline
-  \textbf{PCCR14} & \textbf{ST\_EXT\_CYC} & Cycles used for memory stores to EXT. Every non-TCDM access is considered external \\ \hline
-  \textbf{PCCR15} & \textbf{TCDM\_CONT}   & Cycles wasted due to TCDM/log-interconnect contention \\ \hline
+  \textbf{PCCR11} & \textbf{LD\_EXT}      & Number of memory loads to EXT executed. Misaligned accesses are counted twice. Every non-TCDM access is considered external (PULP only) \\ \hline
+  \textbf{PCCR12} & \textbf{ST\_EXT}      & Number of memory stores to EXT executed. Misaligned accesses are counted twice. Every non-TCDM access is considered external (PULP only) \\ \hline
+  \textbf{PCCR13} & \textbf{LD\_EXT\_CYC} & Cycles used for memory loads to EXT. Every non-TCDM access is considered external (PULPY only) \\ \hline
+  \textbf{PCCR14} & \textbf{ST\_EXT\_CYC} & Cycles used for memory stores to EXT. Every non-TCDM access is considered external (PULPY only) \\ \hline
+  \textbf{PCCR15} & \textbf{TCDM\_CONT}   & Cycles wasted due to TCDM/log-interconnect contention (PULPY only) \\ \hline
   \textbf{PCCR31} & \textbf{ALL}          & Special Register, a write to this register will set all counters to the supplied value\\ \bottomrule
 \end{tabularx}
 \end{table}