diff --git a/ci/vars.yml b/ci/vars.yml index 2b0feaae..0768ede0 100644 --- a/ci/vars.yml +++ b/ci/vars.yml @@ -13,4 +13,4 @@ variables: RISCV_COMPLIANCE_GIT_VERSION: "844c6660ef3f0d9b96957991109dfd80cc4938e2" VERIBLE_VERSION: "v0.0-1213-g9e5c085" # lowRISC-internal version numbers of Ibex-specific Spike builds. - SPIKE_IBEX_VERSION: "20211027-git-ec461195803d0a8a72c90d52dbb38ad24ac7c55d" + SPIKE_IBEX_VERSION: "20220308-git-20a886cba76dd80a23b548743ab3c73b19f65e41" diff --git a/doc/03_reference/cosim.rst b/doc/03_reference/cosim.rst index f6eef5c8..3c9eb880 100644 --- a/doc/03_reference/cosim.rst +++ b/doc/03_reference/cosim.rst @@ -25,7 +25,7 @@ It is disabled by default in the UVM DV environment currently, however it is int Setup and Usage --------------- -Clone the `lowRISC fork of Spike `_ and check out the ``ibex-cosim-v0.1`` tag. +Clone the `lowRISC fork of Spike `_ and check out the ``ibex-cosim-v0.2`` tag. Other, later, versions called ``ibex-cosim-v*`` may also work but there's no guarantee of backwards compatibility. Follow the Spike build instructions to build and install Spike. The build will install multiple header files and libraries, it is recommended a custom install location (using ``--prefix=`` with ``configure``) is used to avoid cluttering system directories. diff --git a/doc/03_reference/verification.rst b/doc/03_reference/verification.rst index 7835acb8..0f900408 100644 --- a/doc/03_reference/verification.rst +++ b/doc/03_reference/verification.rst @@ -96,16 +96,20 @@ In order to run the co-simulation flow, you'll need: - The Spike RISC-V instruction set simulator + lowRISC maintains a `lowRISC-specific Spike fork `_, needed to model: + + Cosimulation (needed for verification) + + Some custom CSRs + + Custom NMI behavior + + Ibex verification should work with the Spike version that is tagged as ``ibex-cosim-v0.2``. + Other, later, versions called ``ibex-cosim-v*`` may also work but there's no guarantee of backwards compatibility. + Spike must be built with the ``--enable-commitlog`` and ``--enable-misaligned`` options. ``--enable-commitlog`` is needed to produce log output to track the instructions that were executed. ``--enable-misaligned`` tells Spike to simulate a core that handles misaligned accesses in hardware (rather than jumping to a trap handler). - Ibex supports v.1.0.0 of the RISC-V Bit-Manipulation Extension together with the remaining sub-extensions of draft v.0.93 of the bitmanip spec. - lowRISC maintains a `lowRISC-specific branch of Spike `_ that matches the supported Bitmanip specification plus some custom CSRs. - This branch must also be used in order to to simulate the core with the Icache enabled. - Note that Ibex used to support the commercial OVPsim simulator. - This is not currently possble because OVPsim doesn't support the co-simulation approach that we use. + This is not currently possible because OVPsim doesn't support the co-simulation approach that we use. - A working RISC-V toolchain (to compile / assemble the generated programs before simulating them). @@ -123,7 +127,7 @@ to tell the RISCV-DV code where to find them: export RISCV_OBJCOPY="$RISCV_TOOLCHAIN/bin/riscv32-unknown-elf-objcopy" export SPIKE_PATH=/path/to/spike/bin -.. _LRSpike: https://github.com/lowRISC/riscv-isa-sim/tree/ibex_cosim +.. _LRSpike: https://github.com/lowRISC/riscv-isa-sim .. _riscv-toolchain-source: https://github.com/riscv/riscv-gnu-toolchain .. _riscv-toolchain-releases: https://github.com/lowRISC/lowrisc-toolchains/releases .. _bitmanip-patches: https://github.com/lowRISC/lowrisc-toolchains#how-to-generate-the-bitmanip-patches