diff --git a/cs_registers.sv b/cs_registers.sv index 65ea1191..967f112a 100644 --- a/cs_registers.sv +++ b/cs_registers.sv @@ -52,7 +52,7 @@ module cs_registers output logic irq_enable_o, output logic [31:0] epcr_o, - output logic timer_cmp_irq_o, + // Performance Counters input logic stall_id_i, // stall ID stage input logic is_compressed_i, // compressed instruction in ID @@ -100,9 +100,6 @@ module cs_registers // Generic CSRs logic [31:0] csr [0:`CSR_MAX_IDX]; logic [31:0] csr_n [0:`CSR_MAX_IDX]; - - // mtime - cycle count - //logic [31:0] csr_mtime_int, csr_mtime; // CSR update logic logic [31:0] csr_wdata_int; @@ -111,11 +108,11 @@ module cs_registers // Interrupt control signals logic irq_enable, irq_enable_n; - + //////////////////////////////////////////// // ____ ____ ____ ____ // - // / ___/ ___|| _ \ | _ \ ___ __ _ // + // / ___/ ___|| _ \ | _ \ ___ __ _ // // | | \___ \| |_) | | |_) / _ \/ _` | // // | |___ ___) | _ < | _ < __/ (_| | // // \____|____/|_| \_\ |_| \_\___|\__, | // @@ -142,15 +139,6 @@ module cs_registers 12'hF01: csr_rdata_int = 32'h00_00_80_00; // mhartid: unique hardware thread id 12'hF10: csr_rdata_int = {22'b0, cluster_id_i, core_id_i}; - - // Machine trap setup 0x300 - 0x321 - // mtimecmp - machine wall-clock timer compare value - 12'h321: csr_rdata_int = csr[`CSR_IDX_MTIMECMP]; - - // machine level timers and counters 0x701 - 0x741 - // mtime - machine wall-clock time (? - actually not really wall clock??) - 12'h701: csr_rdata_int = csr[`CSR_IDX_MTIME]; - endcase end @@ -159,9 +147,6 @@ module cs_registers always_comb begin csr_n = csr; - //if timer interrupt occured - reset status unless it is written by the application - if (timer_cmp_irq_o == 1'b1) csr_n[`CSR_IDX_MTIME] = 32'b0; - irq_enable_n = irq_enable; case (csr_addr_i) @@ -172,12 +157,6 @@ module cs_registers 12'h340: if (csr_we_int) csr_n[`CSR_IDX_MSCRATCH] = csr_wdata_int; // mepc: exception program counter 12'h341: if (csr_we_int) csr_n[`CSR_IDX_MEPC] = csr_wdata_int; - - // mtimecmp - 12'h321: if (csr_we_int) csr_n[`CSR_IDX_MTIMECMP] = csr_wdata_int; - - // mtime - 12'h701: if (csr_we_int) csr_n[`CSR_IDX_MTIME] = csr_wdata_int; endcase end @@ -229,8 +208,6 @@ module cs_registers begin // update CSRs csr <= csr_n; - // increment the timer register (mtime) - csr[`CSR_IDX_MTIME] <= csr_n[`CSR_IDX_MTIME] + 1; irq_enable <= irq_enable_n; // exception PC writes from exception controller get priority @@ -240,31 +217,6 @@ module cs_registers csr[`CSR_IDX_MEPC] <= curr_pc_id_i; end end - - //////////////////////////////////////////////// - // _____ _ ____ // - // |_ _(_)_ __ ___ / ___|_ __ ___ _ __ // - // | | | | '_ ` _ \ | | | '_ ` _ \| '_ \ // - // | | | | | | | | || |___| | | | | | |_) | // - // |_| |_|_| |_| |_(_)____|_| |_| |_| .__/ // - // |_| // - // // - //////////////////////////////////////////////// - - // ommitting timer interrupt status register according to spec 1.7 priv instr. - // 32bit comparator - always_comb - begin - if (csr[`CSR_IDX_MTIMECMP] != 32'b0 && csr[`CSR_IDX_MTIMECMP] == csr[`CSR_IDX_MTIME]) - begin - timer_cmp_irq_o = 1'b1; - end - else - begin - timer_cmp_irq_o = 1'b0; - end - end - ///////////////////////////////////////////////////////////////// // ____ __ ____ _ // diff --git a/decoder.sv b/decoder.sv index 17137990..a78e30f7 100644 --- a/decoder.sv +++ b/decoder.sv @@ -27,7 +27,7 @@ `include "defines.sv" -module decoder +module riscv_decoder ( // singals running to/from controller input logic deassert_we_i, // deassert we, we are stalled or not active diff --git a/exc_controller.sv b/exc_controller.sv index 1d6c6a64..c1807fd6 100644 --- a/exc_controller.sv +++ b/exc_controller.sv @@ -140,7 +140,7 @@ module exc_controller exc_reason = ExcIllegalInsn; end - if (exc_reason_q != ExcNone) + if (exc_reason_q != ExcNone) exc_reason = exc_reason_q; end @@ -165,14 +165,14 @@ module exc_controller unique case (exc_reason) // an IRQ is present, execute pending jump and then go // to the ISR without flushing the pipeline - ExcIR: begin + ExcIR: begin if (((jump_in_id_i == `BRANCH_JALR || jump_in_id_i == `BRANCH_JAL) && new_instr_id_q == 1'b0) || jump_in_ex_i == `BRANCH_COND) begin //wait one cycle - if (~stall_id_i) - exc_reason_n = ExcIRDeferred; - end + if (~stall_id_i) + exc_reason_n = ExcIRDeferred; + end else //don't wait begin exc_pc_sel_o = 1'b1; @@ -189,29 +189,24 @@ module exc_controller if (jump_in_id_i != `BRANCH_NONE) save_pc_id_o = 1'b1; else - save_pc_if_o = 1'b1; + save_pc_if_o = 1'b1; end end - - ExcIRDeferred : begin - - + ExcIRDeferred : begin // jumps in ex stage already taken if (jump_in_id_i != `BRANCH_NONE) save_pc_id_o = 1'b1; else - save_pc_if_o = 1'b1; + save_pc_if_o = 1'b1; - exc_pc_sel_o = 1'b1; if (irq_nm_i == 1'b1) // emergency IRQ has higher priority exc_pc_mux_o = `EXC_PC_IRQ_NM; - else if (irq_i == 1'b1) + else // irq_i == 1'b1 exc_pc_mux_o = `EXC_PC_IRQ; - else //irq_timer_cmp_i == 1'b1 - exc_pc_mux_o = `EXC_PC_MTIME_CMP; + exc_running_n = 1'b1; end diff --git a/id_stage.sv b/id_stage.sv index 7b6ea0bc..3852980f 100644 --- a/id_stage.sv +++ b/id_stage.sv @@ -530,7 +530,7 @@ module id_stage // // /////////////////////////////////////////////// - decoder decoder_i + riscv_decoder decoder_i ( // controller related signals .deassert_we_i ( deassert_we ),