diff --git a/controller.sv b/controller.sv index 6dc26ef3..b24c985b 100644 --- a/controller.sv +++ b/controller.sv @@ -68,8 +68,6 @@ module controller output logic mult_use_carry_o, // Use carry for MAC output logic mult_mac_en_o, // Use the accumulator after multiplication - output logic regfile_wdata_mux_sel_o, // Mul selctor used in WB stage to select regfile wdata from ex result (ALU-MUL), from data memory, or special registers - input logic regfile_wdata_mux_sel_ex_i, // FW signal: Mul selctor used in WB stage to select regfile wdata from ex result (ALU-MUL), from data memory, or special registers output logic regfile_we_o, // Write Enable to regfile output logic [1:0] regfile_alu_waddr_mux_sel_o, // Select register write address for ALU/MUL operations @@ -208,7 +206,6 @@ module controller mult_use_carry_o = 1'b0; mult_mac_en_o = 1'b0; - regfile_wdata_mux_sel_o = 1'b1; // TODO: Remove, no longer used regfile_we = 1'b0; regfile_alu_we = 1'b0; regfile_alu_waddr_mux_sel_o = 2'b01; diff --git a/ex_stage.sv b/ex_stage.sv index ec0e8e68..1e15e76a 100644 --- a/ex_stage.sv +++ b/ex_stage.sv @@ -69,7 +69,6 @@ module ex_stage // directly passed through to WB stage, not used in EX input logic regfile_we_i, input logic [4:0] regfile_waddr_i, - input logic regfile_wdata_mux_sel_i, input logic [31:0] regfile_rb_data_i, @@ -83,7 +82,6 @@ module ex_stage // Output of EX stage pipeline output logic [4:0] regfile_waddr_wb_o, - output logic regfile_wdata_mux_sel_wb_o, output logic regfile_we_wb_o, output logic [31:0] regfile_rb_data_wb_o, @@ -220,7 +218,6 @@ module ex_stage if (rst_n == 1'b0) begin regfile_waddr_wb_o <= 5'b0_0000; - regfile_wdata_mux_sel_wb_o <= 1'b0; regfile_we_wb_o <= 1'b0; regfile_rb_data_wb_o <= 32'h0000_0000; end @@ -230,7 +227,6 @@ module ex_stage begin regfile_we_wb_o <= regfile_we_i; regfile_waddr_wb_o <= regfile_waddr_i; - regfile_wdata_mux_sel_wb_o <= regfile_wdata_mux_sel_i; regfile_rb_data_wb_o <= regfile_rb_data_i; end end diff --git a/id_stage.sv b/id_stage.sv index 0dbff8e2..851f114f 100644 --- a/id_stage.sv +++ b/id_stage.sv @@ -85,7 +85,6 @@ module id_stage output logic mult_mac_en_ex_o, output logic [4:0] regfile_waddr_ex_o, - output logic regfile_wdata_mux_sel_ex_o, output logic regfile_we_ex_o, output logic [4:0] regfile_alu_waddr_ex_o, @@ -232,7 +231,6 @@ module id_stage logic mult_mac_en; // Enables the use of the accumulator // Register Write Control - logic regfile_wdata_mux_sel; logic regfile_we_id; logic [1:0] regfile_alu_waddr_mux_sel; // TODO: FixMe -> 1bit @@ -567,8 +565,6 @@ module id_stage .mult_mac_en_o ( mult_mac_en ), // Register file control signals - .regfile_wdata_mux_sel_o ( regfile_wdata_mux_sel ), - .regfile_wdata_mux_sel_ex_i ( regfile_wdata_mux_sel_ex_o ), .regfile_we_o ( regfile_we_id ), .regfile_alu_we_o ( regfile_alu_we_id ), @@ -765,7 +761,6 @@ module id_stage mult_mac_en_ex_o <= 1'b0; regfile_waddr_ex_o <= 5'b0; - regfile_wdata_mux_sel_ex_o <= 1'b0; regfile_we_ex_o <= 1'b0; regfile_alu_waddr_ex_o <= 5'b0; @@ -833,7 +828,6 @@ module id_stage regfile_waddr_ex_o <= regfile_waddr_id; - regfile_wdata_mux_sel_ex_o <= regfile_wdata_mux_sel; regfile_we_ex_o <= regfile_we_id; regfile_alu_waddr_ex_o <= regfile_alu_waddr_id; diff --git a/riscv_core.sv b/riscv_core.sv index b43be4f4..67796473 100644 --- a/riscv_core.sv +++ b/riscv_core.sv @@ -130,12 +130,10 @@ module riscv_core // Register Write Control logic [4:0] regfile_waddr_ex; - logic regfile_wdata_mux_sel_ex; logic regfile_we_ex; logic [4:0] regfile_waddr_fw_wb_o; // From WB to ID logic regfile_we_wb; logic [31:0] regfile_wdata; - logic regfile_wdata_mux_sel_wb; logic [4:0] regfile_alu_waddr_ex; logic regfile_alu_we_ex; @@ -163,7 +161,6 @@ module riscv_core logic [31:0] data_addr_ex; logic data_misaligned_ex; logic [31:0] data_rdata_int; - logic [31:0] lsu_data_reg; logic data_ack_int; // Signals between instruction core interface and pipe (if and id stages) @@ -379,7 +376,6 @@ module riscv_core .mult_mac_en_ex_o ( mult_mac_en_ex ), // from ID to EX stage .regfile_waddr_ex_o ( regfile_waddr_ex ), - .regfile_wdata_mux_sel_ex_o ( regfile_wdata_mux_sel_ex ), .regfile_we_ex_o ( regfile_we_ex ), .regfile_alu_we_ex_o ( regfile_alu_we_ex ), @@ -494,7 +490,6 @@ module riscv_core // From ID Stage: Regfile control signals .regfile_waddr_i ( regfile_waddr_ex ), - .regfile_wdata_mux_sel_i ( regfile_wdata_mux_sel_ex ), .regfile_we_i ( regfile_we_ex ), .regfile_alu_we_i ( regfile_alu_we_ex ), @@ -510,7 +505,6 @@ module riscv_core // Output of ex stage pipeline .regfile_waddr_wb_o ( regfile_waddr_fw_wb_o ), - .regfile_wdata_mux_sel_wb_o ( regfile_wdata_mux_sel_wb ), .regfile_we_wb_o ( regfile_we_wb ), .regfile_rb_data_wb_o ( regfile_rb_data_wb ), @@ -545,13 +539,11 @@ module riscv_core // \_/\_/ |____/ |____/ |_/_/ \_\____|_____| // // // ///////////////////////////////////////////////////////// + // TODO: the wb stage does absolutely nothing anymore, consider removing it wb_stage wb_stage_i ( - // Mux selector of regfile wdata - .regfile_wdata_mux_sel_i ( regfile_wdata_mux_sel_wb ), // Mux inputs .data_rdata_i ( data_rdata_int ), - .lsu_data_reg_i ( lsu_data_reg ), // Mux output .regfile_wdata_o ( regfile_wdata ) ); @@ -578,7 +570,6 @@ module riscv_core .data_sign_ext_ex_i ( data_sign_ext_ex ), // sign extension .data_rdata_ex_o ( data_rdata_int ), - .lsu_data_reg_o ( lsu_data_reg ), .data_req_ex_i ( data_req_ex ), .data_addr_ex_i ( data_addr_ex ), .data_ack_int_o ( data_ack_int ), // ack used in controller to stall diff --git a/wb_stage.sv b/wb_stage.sv index a4484e9d..c3613461 100644 --- a/wb_stage.sv +++ b/wb_stage.sv @@ -37,29 +37,14 @@ module wb_stage ( - // MUX SELECTOR --> Used to select what write in the register file - input logic regfile_wdata_mux_sel_i, // Comes from the controller (thru id-ex and ex-wb pipe) - // MUX INPUTS input logic [31:0] data_rdata_i, // read Data from data memory system - input logic [31:0] lsu_data_reg_i, // TODO: remove; read data registered in LSU + // MUX OUTPUT output logic [31:0] regfile_wdata_o // write data for register file ); - // TODO: Remove this mux and the associated signals - // Register Write Data Selection --> Data to write in the regfile - // Select between: - // 0: From Special Register - // 1: From Data Memory - always_comb - begin : REGFILE_WDATA_MUX - case (regfile_wdata_mux_sel_i) - //1'b0: regfile_wdata_o = sp_rdata_i; - 1'b1: regfile_wdata_o = data_rdata_i; - default: regfile_wdata_o = data_rdata_i; - endcase; // case (regfile_wdata_mux_sel_i) - end + assign regfile_wdata_o = data_rdata_i; endmodule