diff --git a/doc/02_user/integration.rst b/doc/02_user/integration.rst
index 018ed7ae..94de1016 100644
--- a/doc/02_user/integration.rst
+++ b/doc/02_user/integration.rst
@@ -66,6 +66,7 @@ Instantiation Template
 
       // Debug interface
       .debug_req_i    (),
+      .crash_dump_o   (),
 
       // Special control signals
       .fetch_enable_i (),
@@ -171,6 +172,8 @@ Interfaces
 | ``irq_*``               | Interrupt inputs, see :ref:`exceptions-interrupts`                     |
 +-------------------------+------------------------------------------------------------------------+
 | ``debug_*``             | Debug interface, see :ref:`debug-support`                              |
++-------------------------+------------------------------------------------------------------------+
+| ``crash_dump_o``        | A set of signals that can be captured on reset to aid crash debugging. |
 +-------------------------+-------------------------+-----+----------------------------------------+
 | ``fetch_enable_i``      | 1                       | in  | When it comes out of reset, the core   |
 |                         |                         |     | will not start fetching and executing  |
diff --git a/dv/riscv_compliance/rtl/ibex_riscv_compliance.sv b/dv/riscv_compliance/rtl/ibex_riscv_compliance.sv
index 44d1044a..cc37bce5 100644
--- a/dv/riscv_compliance/rtl/ibex_riscv_compliance.sv
+++ b/dv/riscv_compliance/rtl/ibex_riscv_compliance.sv
@@ -161,6 +161,7 @@ module ibex_riscv_compliance (
       .irq_nm_i       (1'b0              ),
 
       .debug_req_i    ('b0               ),
+      .crash_dump_o   (                  ),
 
       .fetch_enable_i ('b1               ),
       .alert_minor_o  (                  ),
diff --git a/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv b/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv
index afe9da6a..5dcb539c 100644
--- a/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv
+++ b/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv
@@ -106,6 +106,7 @@ module core_ibex_tb_top;
     .irq_nm_i       (irq_vif.irq_nm       ),
 
     .debug_req_i    (dut_if.debug_req     ),
+    .crash_dump_o   (                     ),
 
     .fetch_enable_i (dut_if.fetch_enable  ),
     .alert_minor_o  (dut_if.alert_minor   ),
diff --git a/examples/fpga/artya7/rtl/top_artya7.sv b/examples/fpga/artya7/rtl/top_artya7.sv
index c26ca459..ef50ceb2 100644
--- a/examples/fpga/artya7/rtl/top_artya7.sv
+++ b/examples/fpga/artya7/rtl/top_artya7.sv
@@ -80,6 +80,7 @@ module top_artya7 (
      .irq_nm_i              (1'b0),
 
      .debug_req_i           ('b0),
+     .crash_dump_o          (),
 
      .fetch_enable_i        ('b1),
      .alert_minor_o         (),
diff --git a/examples/simple_system/rtl/ibex_simple_system.sv b/examples/simple_system/rtl/ibex_simple_system.sv
index 6d902ec7..debf4c2a 100644
--- a/examples/simple_system/rtl/ibex_simple_system.sv
+++ b/examples/simple_system/rtl/ibex_simple_system.sv
@@ -212,6 +212,7 @@ module ibex_simple_system (
       .irq_nm_i              (1'b0),
 
       .debug_req_i           ('b0),
+      .crash_dump_o          (),
 
       .fetch_enable_i        ('b1),
       .alert_minor_o         (),
diff --git a/rtl/ibex_core.sv b/rtl/ibex_core.sv
index aafc06fb..11665f64 100644
--- a/rtl/ibex_core.sv
+++ b/rtl/ibex_core.sv
@@ -34,77 +34,78 @@ module ibex_core #(
     parameter int unsigned        DmExceptionAddr  = 32'h1A110808
 ) (
     // Clock and Reset
-    input  logic        clk_i,
-    input  logic        rst_ni,
+    input  logic                  clk_i,
+    input  logic                  rst_ni,
 
-    input  logic        test_en_i,     // enable all clock gates for testing
+    input  logic                  test_en_i,     // enable all clock gates for testing
 
-    input  logic [31:0] hart_id_i,
-    input  logic [31:0] boot_addr_i,
+    input  logic [31:0]           hart_id_i,
+    input  logic [31:0]           boot_addr_i,
 
     // Instruction memory interface
-    output logic        instr_req_o,
-    input  logic        instr_gnt_i,
-    input  logic        instr_rvalid_i,
-    output logic [31:0] instr_addr_o,
-    input  logic [31:0] instr_rdata_i,
-    input  logic        instr_err_i,
+    output logic                  instr_req_o,
+    input  logic                  instr_gnt_i,
+    input  logic                  instr_rvalid_i,
+    output logic [31:0]           instr_addr_o,
+    input  logic [31:0]           instr_rdata_i,
+    input  logic                  instr_err_i,
 
     // Data memory interface
-    output logic        data_req_o,
-    input  logic        data_gnt_i,
-    input  logic        data_rvalid_i,
-    output logic        data_we_o,
-    output logic [3:0]  data_be_o,
-    output logic [31:0] data_addr_o,
-    output logic [31:0] data_wdata_o,
-    input  logic [31:0] data_rdata_i,
-    input  logic        data_err_i,
+    output logic                  data_req_o,
+    input  logic                  data_gnt_i,
+    input  logic                  data_rvalid_i,
+    output logic                  data_we_o,
+    output logic [3:0]            data_be_o,
+    output logic [31:0]           data_addr_o,
+    output logic [31:0]           data_wdata_o,
+    input  logic [31:0]           data_rdata_i,
+    input  logic                  data_err_i,
 
     // Interrupt inputs
-    input  logic        irq_software_i,
-    input  logic        irq_timer_i,
-    input  logic        irq_external_i,
-    input  logic [14:0] irq_fast_i,
-    input  logic        irq_nm_i,       // non-maskeable interrupt
+    input  logic                  irq_software_i,
+    input  logic                  irq_timer_i,
+    input  logic                  irq_external_i,
+    input  logic [14:0]           irq_fast_i,
+    input  logic                  irq_nm_i,       // non-maskeable interrupt
 
     // Debug Interface
-    input  logic        debug_req_i,
+    input  logic                  debug_req_i,
+    output ibex_pkg::crash_dump_t crash_dump_o,
 
     // RISC-V Formal Interface
     // Does not comply with the coding standards of _i/_o suffixes, but follows
     // the convention of RISC-V Formal Interface Specification.
 `ifdef RVFI
-    output logic        rvfi_valid,
-    output logic [63:0] rvfi_order,
-    output logic [31:0] rvfi_insn,
-    output logic        rvfi_trap,
-    output logic        rvfi_halt,
-    output logic        rvfi_intr,
-    output logic [ 1:0] rvfi_mode,
-    output logic [ 1:0] rvfi_ixl,
-    output logic [ 4:0] rvfi_rs1_addr,
-    output logic [ 4:0] rvfi_rs2_addr,
-    output logic [ 4:0] rvfi_rs3_addr,
-    output logic [31:0] rvfi_rs1_rdata,
-    output logic [31:0] rvfi_rs2_rdata,
-    output logic [31:0] rvfi_rs3_rdata,
-    output logic [ 4:0] rvfi_rd_addr,
-    output logic [31:0] rvfi_rd_wdata,
-    output logic [31:0] rvfi_pc_rdata,
-    output logic [31:0] rvfi_pc_wdata,
-    output logic [31:0] rvfi_mem_addr,
-    output logic [ 3:0] rvfi_mem_rmask,
-    output logic [ 3:0] rvfi_mem_wmask,
-    output logic [31:0] rvfi_mem_rdata,
-    output logic [31:0] rvfi_mem_wdata,
+    output logic                  rvfi_valid,
+    output logic [63:0]           rvfi_order,
+    output logic [31:0]           rvfi_insn,
+    output logic                  rvfi_trap,
+    output logic                  rvfi_halt,
+    output logic                  rvfi_intr,
+    output logic [ 1:0]           rvfi_mode,
+    output logic [ 1:0]           rvfi_ixl,
+    output logic [ 4:0]           rvfi_rs1_addr,
+    output logic [ 4:0]           rvfi_rs2_addr,
+    output logic [ 4:0]           rvfi_rs3_addr,
+    output logic [31:0]           rvfi_rs1_rdata,
+    output logic [31:0]           rvfi_rs2_rdata,
+    output logic [31:0]           rvfi_rs3_rdata,
+    output logic [ 4:0]           rvfi_rd_addr,
+    output logic [31:0]           rvfi_rd_wdata,
+    output logic [31:0]           rvfi_pc_rdata,
+    output logic [31:0]           rvfi_pc_wdata,
+    output logic [31:0]           rvfi_mem_addr,
+    output logic [ 3:0]           rvfi_mem_rmask,
+    output logic [ 3:0]           rvfi_mem_wmask,
+    output logic [31:0]           rvfi_mem_rdata,
+    output logic [31:0]           rvfi_mem_wdata,
 `endif
 
     // CPU Control Signals
-    input  logic        fetch_enable_i,
-    output logic        alert_minor_o,
-    output logic        alert_major_o,
-    output logic        core_sleep_o
+    input  logic                  fetch_enable_i,
+    output logic                  alert_minor_o,
+    output logic                  alert_major_o,
+    output logic                  core_sleep_o
 );
 
   import ibex_pkg::*;
@@ -895,6 +896,15 @@ module ibex_core #(
     );
   end
 
+  ///////////////////////
+  // Crash dump output //
+  ///////////////////////
+
+  assign crash_dump_o.current_pc     = pc_id;
+  assign crash_dump_o.next_pc        = pc_if;
+  assign crash_dump_o.last_data_addr = lsu_addr_last;
+  assign crash_dump_o.exception_addr = csr_mepc;
+
   ///////////////////
   // Alert outputs //
   ///////////////////
diff --git a/rtl/ibex_core_tracing.sv b/rtl/ibex_core_tracing.sv
index a14eb5af..96bdc227 100644
--- a/rtl/ibex_core_tracing.sv
+++ b/rtl/ibex_core_tracing.sv
@@ -28,48 +28,49 @@ module ibex_core_tracing #(
     parameter int unsigned        DmExceptionAddr  = 32'h1A110808
 ) (
     // Clock and Reset
-    input  logic        clk_i,
-    input  logic        rst_ni,
+    input  logic                  clk_i,
+    input  logic                  rst_ni,
 
-    input  logic        test_en_i,     // enable all clock gates for testing
+    input  logic                  test_en_i,     // enable all clock gates for testing
 
-    input  logic [31:0] hart_id_i,
-    input  logic [31:0] boot_addr_i,
+    input  logic [31:0]           hart_id_i,
+    input  logic [31:0]           boot_addr_i,
 
     // Instruction memory interface
-    output logic        instr_req_o,
-    input  logic        instr_gnt_i,
-    input  logic        instr_rvalid_i,
-    output logic [31:0] instr_addr_o,
-    input  logic [31:0] instr_rdata_i,
-    input  logic        instr_err_i,
+    output logic                  instr_req_o,
+    input  logic                  instr_gnt_i,
+    input  logic                  instr_rvalid_i,
+    output logic [31:0]           instr_addr_o,
+    input  logic [31:0]           instr_rdata_i,
+    input  logic                  instr_err_i,
 
     // Data memory interface
-    output logic        data_req_o,
-    input  logic        data_gnt_i,
-    input  logic        data_rvalid_i,
-    output logic        data_we_o,
-    output logic [3:0]  data_be_o,
-    output logic [31:0] data_addr_o,
-    output logic [31:0] data_wdata_o,
-    input  logic [31:0] data_rdata_i,
-    input  logic        data_err_i,
+    output logic                  data_req_o,
+    input  logic                  data_gnt_i,
+    input  logic                  data_rvalid_i,
+    output logic                  data_we_o,
+    output logic [3:0]            data_be_o,
+    output logic [31:0]           data_addr_o,
+    output logic [31:0]           data_wdata_o,
+    input  logic [31:0]           data_rdata_i,
+    input  logic                  data_err_i,
 
     // Interrupt inputs
-    input  logic        irq_software_i,
-    input  logic        irq_timer_i,
-    input  logic        irq_external_i,
-    input  logic [14:0] irq_fast_i,
-    input  logic        irq_nm_i,       // non-maskeable interrupt
+    input  logic                  irq_software_i,
+    input  logic                  irq_timer_i,
+    input  logic                  irq_external_i,
+    input  logic [14:0]           irq_fast_i,
+    input  logic                  irq_nm_i,       // non-maskeable interrupt
 
     // Debug Interface
-    input  logic        debug_req_i,
+    input  logic                  debug_req_i,
+    output ibex_pkg::crash_dump_t crash_dump_o,
 
     // CPU Control Signals
-    input  logic        fetch_enable_i,
-    output logic        alert_minor_o,
-    output logic        alert_major_o,
-    output logic        core_sleep_o
+    input  logic                  fetch_enable_i,
+    output logic                  alert_minor_o,
+    output logic                  alert_major_o,
+    output logic                  core_sleep_o
 
 );
 
@@ -157,6 +158,7 @@ module ibex_core_tracing #(
     .irq_nm_i,
 
     .debug_req_i,
+    .crash_dump_o,
 
     .rvfi_valid,
     .rvfi_order,
diff --git a/rtl/ibex_pkg.sv b/rtl/ibex_pkg.sv
index 28171d30..d42b9d2a 100644
--- a/rtl/ibex_pkg.sv
+++ b/rtl/ibex_pkg.sv
@@ -8,6 +8,17 @@
  */
 package ibex_pkg;
 
+////////////////
+// IO Structs //
+////////////////
+
+typedef struct packed {
+  logic [31:0] current_pc;
+  logic [31:0] next_pc;
+  logic [31:0] last_data_addr;
+  logic [31:0] exception_addr;
+} crash_dump_t;
+
 /////////////////////
 // Parameter Enums //
 /////////////////////