diff --git a/dv/uvm/icache/data/ibex_icache_testplan.hjson b/dv/uvm/icache/data/ibex_icache_testplan.hjson
index 8dce92fe..96cd5468 100644
--- a/dv/uvm/icache/data/ibex_icache_testplan.hjson
+++ b/dv/uvm/icache/data/ibex_icache_testplan.hjson
@@ -63,7 +63,7 @@
             and seed updates for the memory to try and hit any race conditions
             between the request tracking logic and the invalidation logic.'''
       milestone: V2
-      tests: []
+      tests: ["ibex_icache_invalidation"]
     }
 
     {
diff --git a/dv/uvm/icache/dv/env/ibex_icache_env.core b/dv/uvm/icache/dv/env/ibex_icache_env.core
index 6a5c7f4a..53d1f8d8 100644
--- a/dv/uvm/icache/dv/env/ibex_icache_env.core
+++ b/dv/uvm/icache/dv/env/ibex_icache_env.core
@@ -22,6 +22,7 @@ filesets:
       - seq_lib/ibex_icache_sanity_vseq.sv: {is_include_file: true}
       - seq_lib/ibex_icache_passthru_vseq.sv: {is_include_file: true}
       - seq_lib/ibex_icache_caching_vseq.sv: {is_include_file: true}
+      - seq_lib/ibex_icache_invalidation_vseq.sv: {is_include_file: true}
     file_type: systemVerilogSource
 
 targets:
diff --git a/dv/uvm/icache/dv/env/seq_lib/ibex_icache_invalidation_vseq.sv b/dv/uvm/icache/dv/env/seq_lib/ibex_icache_invalidation_vseq.sv
new file mode 100644
index 00000000..68b1c7e6
--- /dev/null
+++ b/dv/uvm/icache/dv/env/seq_lib/ibex_icache_invalidation_vseq.sv
@@ -0,0 +1,25 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+class ibex_icache_invalidation_vseq extends ibex_icache_base_vseq;
+
+  `uvm_object_utils(ibex_icache_invalidation_vseq)
+  `uvm_object_new
+
+  virtual task pre_start();
+    super.pre_start();
+
+    // Constrain branch targets and force the cache to be enabled
+    core_seq.constrain_branches = 1'b1;
+    core_seq.initial_enable     = 1'b1;
+    core_seq.const_enable       = 1'b1;
+
+    // Invalidate the cache occasionally. This test is all about checking that invalidation works,
+    // so we don't want it too small, but it only makes sense if we actually have some gaps between
+    // our "bouts of invalidation".
+    core_seq.gap_between_seeds = 19;
+
+  endtask : pre_start
+
+endclass : ibex_icache_invalidation_vseq
diff --git a/dv/uvm/icache/dv/env/seq_lib/ibex_icache_vseq_list.sv b/dv/uvm/icache/dv/env/seq_lib/ibex_icache_vseq_list.sv
index 0032dbab..7c1210d2 100644
--- a/dv/uvm/icache/dv/env/seq_lib/ibex_icache_vseq_list.sv
+++ b/dv/uvm/icache/dv/env/seq_lib/ibex_icache_vseq_list.sv
@@ -6,3 +6,4 @@
 `include "ibex_icache_sanity_vseq.sv"
 `include "ibex_icache_passthru_vseq.sv"
 `include "ibex_icache_caching_vseq.sv"
+`include "ibex_icache_invalidation_vseq.sv"
diff --git a/dv/uvm/icache/dv/ibex_icache_sim_cfg.hjson b/dv/uvm/icache/dv/ibex_icache_sim_cfg.hjson
index b87b3a81..c99f5c77 100644
--- a/dv/uvm/icache/dv/ibex_icache_sim_cfg.hjson
+++ b/dv/uvm/icache/dv/ibex_icache_sim_cfg.hjson
@@ -36,24 +36,28 @@
   uvm_test: ibex_icache_base_test
   uvm_test_seq: ibex_icache_base_vseq
 
+  run_opts: ["+test_timeout_ns=1000000000"]
+
   // List of test specifications.
   tests: [
     {
       name: ibex_icache_sanity
       uvm_test_seq: ibex_icache_sanity_vseq
-      run_opts: ["+test_timeout_ns=1000000000"]
     }
 
     {
       name: ibex_icache_passthru
       uvm_test_seq: ibex_icache_passthru_vseq
-      run_opts: ["+test_timeout_ns=1000000000"]
     }
 
     {
       name: ibex_icache_caching
       uvm_test_seq: ibex_icache_caching_vseq
-      run_opts: ["+test_timeout_ns=1000000000"]
+    }
+
+    {
+      name: ibex_icache_invalidation
+      uvm_test_seq: ibex_icache_invalidation_vseq
     }
   ]
 
@@ -63,7 +67,8 @@
       name: sanity
       tests: ["ibex_icache_sanity",
               "ibex_icache_passthru",
-              "ibex_icache_caching"]
+              "ibex_icache_caching",
+              "ibex_icache_invalidation"]
     }
   ]
 }