diff --git a/controller.sv b/controller.sv
index 4b1a9663..f9c94a05 100644
--- a/controller.sv
+++ b/controller.sv
@@ -62,7 +62,7 @@ module littleriscv_controller
 
   // LSU
   input  logic        data_req_ex_i,              // data memory access is currently performed in EX stage
-  input  logic        data_misaligned_fsm_i,
+  input  logic        data_misaligned_i,
   input  logic        data_load_event_i,
 
   // jump/branch signals
@@ -525,7 +525,7 @@ module littleriscv_controller
     // Forwarding EX -> ID
 
     // for misaligned memory accesses
-    if (data_misaligned_fsm_i)
+    if (data_misaligned_i)
     begin
       operand_a_fw_mux_sel_o  = SEL_MISALIGNED;
       operand_b_fw_mux_sel_o  = SEL_REGFILE;
diff --git a/exc_controller.sv b/exc_controller.sv
index 46bb8a8a..8526f4b2 100644
--- a/exc_controller.sv
+++ b/exc_controller.sv
@@ -88,11 +88,10 @@ module littleriscv_exc_controller
 
 // request for exception/interrupt
 assign int_req_int =   ecall_insn_i
-                   | illegal_insn_i;
-
-assign ext_req_int =   lsu_load_err_i
-                       | lsu_store_err_i
-                       | irq_enable_i & irq_i;
+                   | illegal_insn_i
+                   | lsu_load_err_i
+                   | lsu_store_err_i;
+assign ext_req_int = irq_enable_i & irq_i;
 
 assign req_int = int_req_int | ext_req_int;
 
diff --git a/id_stage.sv b/id_stage.sv
index 16c2af0d..de616003 100644
--- a/id_stage.sv
+++ b/id_stage.sv
@@ -254,7 +254,6 @@ module littleriscv_id_stage
   logic [1:0]  data_reg_offset_id;
   logic        data_req_id;
   logic        data_load_event_id;
-  logic        data_misaligned_fsm;
 
   // CSR control
   logic        csr_access;
@@ -364,18 +363,17 @@ module littleriscv_id_stage
       endcase
     end
 
+
   // Operand a forwarding mux
   always_comb
     begin : operand_a_fw_mux
       case (operand_a_fw_mux_sel)
         SEL_MISALIGNED:    operand_a_fw_id = misaligned_addr_i;
-        SEL_FW_WB:    operand_a_fw_id = regfile_wdata_wb_i;
-        SEL_REGFILE:  operand_a_fw_id = regfile_data_ra_id;
-        default:       operand_a_fw_id = regfile_data_ra_id;
+        SEL_REGFILE:       operand_a_fw_id = regfile_data_ra_id;
+        default:           operand_a_fw_id = regfile_data_ra_id;
       endcase; // case (operand_a_fw_mux_sel)
     end
 
-
   //////////////////////////////////////////////////////
   //   ___                                 _   ____   //
   //  / _ \ _ __   ___ _ __ __ _ _ __   __| | | __ )  //
@@ -428,7 +426,7 @@ module littleriscv_id_stage
 
     assign alu_operand_b = operand_b;
 
-
+/*
   // Operand b forwarding mux
   always_comb
     begin : operand_b_fw_mux
@@ -438,7 +436,9 @@ module littleriscv_id_stage
         default:       operand_b_fw_id = regfile_data_rb_id;
       endcase; // case (operand_b_fw_mux_sel)
     end
+*/
 
+assign operand_b_fw_id = regfile_data_rb_id;
 
   //////////////////////////////////////////////////////
   //   ___                                 _    ____  //
@@ -598,7 +598,7 @@ module littleriscv_id_stage
 
     // LSU
     .data_req_ex_i                  ( data_req_ex_o          ),
-    .data_misaligned_fsm_i          ( data_misaligned_fsm    ),
+    .data_misaligned_i              ( data_misaligned_i      ),
     .data_load_event_i              ( data_load_event_ex_o   ),
 
     // jump/branch control
diff --git a/load_store_unit.sv b/load_store_unit.sv
index 1a70ba42..19135e5b 100644
--- a/load_store_unit.sv
+++ b/load_store_unit.sv
@@ -344,8 +344,8 @@ module littleriscv_load_store_unit
 
 
 
-  assign load_err_o    = data_gnt_i && data_err_i && ~data_we_o;
-  assign store_err_o   = data_gnt_i && data_err_i && data_we_o;
+  assign load_err_o    = 1'b0;
+  assign store_err_o   = 1'b0;
 
   // FSM
   always_comb