From fde6e505df1625ea3db5ec4c2c980f814df01793 Mon Sep 17 00:00:00 2001 From: Pirmin Vogel Date: Thu, 9 May 2019 18:47:38 +0100 Subject: [PATCH] Make sure all inputs/outputs use _i/_o suffices --- rtl/ibex_controller.sv | 10 +- rtl/ibex_core.sv | 179 ++++++++++++++++----------------- rtl/ibex_cs_registers.sv | 13 ++- rtl/ibex_ex_block.sv | 12 +-- rtl/ibex_fetch_fifo.sv | 10 +- rtl/ibex_id_stage.sv | 28 +++--- rtl/ibex_if_stage.sv | 20 ++-- rtl/ibex_int_controller.sv | 8 +- rtl/ibex_load_store_unit.sv | 21 ++-- rtl/ibex_multdiv_fast.sv | 8 +- rtl/ibex_multdiv_slow.sv | 8 +- rtl/ibex_prefetch_buffer.sv | 12 +-- rtl/ibex_register_file.sv | 10 +- rtl/ibex_register_file_ff.sv | 8 +- rtl/ibex_tracer.sv | 188 +++++++++++++++++------------------ 15 files changed, 267 insertions(+), 268 deletions(-) diff --git a/rtl/ibex_controller.sv b/rtl/ibex_controller.sv index 0ab73ebd..6c49e7ee 100644 --- a/rtl/ibex_controller.sv +++ b/rtl/ibex_controller.sv @@ -24,8 +24,8 @@ * Main CPU controller of the processor */ module ibex_controller ( - input logic clk, - input logic rst_n, + input logic clk_i, + input logic rst_ni, input logic fetch_enable_i, // Start the decoding output logic ctrl_busy_o, // Core is busy processing instructions @@ -126,7 +126,7 @@ module ibex_controller ( // synopsys translate_off // make sure we are called later so that we do not generate messages for // glitches - always_ff @(negedge clk) begin + always_ff @(negedge clk_i) begin // print warning in case of decoding errors if (is_decoding_o && illegal_insn_i) begin $display("%t: Illegal instruction (core %0d) at PC 0x%h: 0x%h", $time, ibex_core.core_id_i, @@ -498,8 +498,8 @@ module ibex_controller ( assign operand_a_fw_mux_sel_o = data_misaligned_i ? SEL_MISALIGNED : SEL_REGFILE; // update registers - always_ff @(posedge clk, negedge rst_n) begin : UPDATE_REGS - if (!rst_n) begin + always_ff @(posedge clk_i, negedge rst_ni) begin : UPDATE_REGS + if (!rst_ni) begin ctrl_fsm_cs <= RESET; //jump_done_q <= 1'b0; debug_mode_q <= 1'b0; diff --git a/rtl/ibex_core.sv b/rtl/ibex_core.sv index f6f3cfdd..efcf62c1 100644 --- a/rtl/ibex_core.sv +++ b/rtl/ibex_core.sv @@ -181,6 +181,8 @@ module ibex_core #( logic perf_jump; logic perf_branch; logic perf_tbranch; + logic perf_load; + logic perf_store; ////////////////////// @@ -225,8 +227,8 @@ module ibex_core #( .DM_HALT_ADDRESS ( DM_HALT_ADDRESS ), .DM_EXCEPTION_ADDRESS ( DM_EXCEPTION_ADDRESS ) ) if_stage_i ( - .clk ( clk ), - .rst_n ( rst_ni ), + .clk_i ( clk ), + .rst_ni ( rst_ni ), // boot address (trap vector location) .boot_addr_i ( boot_addr_i ), @@ -279,8 +281,8 @@ module ibex_core #( .RV32E(RV32E), .RV32M(RV32M) ) id_stage_i ( - .clk ( clk ), - .rst_n ( rst_ni ), + .clk_i ( clk ), + .rst_ni ( rst_ni ), .test_en_i ( test_en_i ), @@ -385,8 +387,8 @@ module ibex_core #( //if you want a SLOW or FAST multiplier .RV32M(RV32M) ) ex_block_i ( - .clk ( clk ), - .rst_n ( rst_ni ), + .clk_i ( clk ), + .rst_ni ( rst_ni ), // Alu signals from ID stage //TODO: hot encoding .alu_operator_i ( alu_operator_ex ), @@ -417,8 +419,8 @@ module ibex_core #( ///////////////////// ibex_load_store_unit load_store_unit_i ( - .clk ( clk ), - .rst_n ( rst_ni ), + .clk_i ( clk ), + .rst_ni ( rst_ni ), //output to data memory .data_req_o ( data_req_o ), @@ -462,121 +464,120 @@ module ibex_core #( // CSRs (Control and Status Registers) // ///////////////////////////////////////// + assign csr_access = csr_access_ex; + assign csr_wdata = alu_operand_a_ex; + assign csr_op = csr_op_ex; + assign csr_addr = csr_num_e'(csr_access_ex ? alu_operand_b_ex[11:0] : 12'b0); + + assign perf_load = data_req_o & data_gnt_i & (~data_we_o); + assign perf_store = data_req_o & data_gnt_i & data_we_o; + ibex_cs_registers #( .N_EXT_CNT ( N_EXT_PERF_COUNTERS ), .RV32E ( RV32E ), .RV32M ( RV32M ) ) cs_registers_i ( - .clk ( clk ), - .rst_n ( rst_ni ), + .clk_i ( clk ), + .rst_ni ( rst_ni ), // Core and Cluster ID from outside - .core_id_i ( core_id_i ), - .cluster_id_i ( cluster_id_i ), + .core_id_i ( core_id_i ), + .cluster_id_i ( cluster_id_i ), // boot address - .boot_addr_i ( boot_addr_i ), + .boot_addr_i ( boot_addr_i ), // Interface to CSRs (SRAM like) - .csr_access_i ( csr_access ), - .csr_addr_i ( csr_addr ), - .csr_wdata_i ( csr_wdata ), - .csr_op_i ( csr_op ), - .csr_rdata_o ( csr_rdata ), + .csr_access_i ( csr_access ), + .csr_addr_i ( csr_addr ), + .csr_wdata_i ( csr_wdata ), + .csr_op_i ( csr_op ), + .csr_rdata_o ( csr_rdata ), // Interrupt related control signals - .m_irq_enable_o ( m_irq_enable ), - .mepc_o ( mepc ), + .m_irq_enable_o ( m_irq_enable ), + .mepc_o ( mepc ), // debug - .debug_cause_i ( debug_cause ), - .debug_csr_save_i ( debug_csr_save ), - .depc_o ( depc ), - .debug_single_step_o ( debug_single_step ), - .debug_ebreakm_o ( debug_ebreakm ), + .debug_cause_i ( debug_cause ), + .debug_csr_save_i ( debug_csr_save ), + .depc_o ( depc ), + .debug_single_step_o ( debug_single_step ), + .debug_ebreakm_o ( debug_ebreakm ), - .pc_if_i ( pc_if ), - .pc_id_i ( pc_id ), + .pc_if_i ( pc_if ), + .pc_id_i ( pc_id ), - .csr_save_if_i ( csr_save_if ), - .csr_save_id_i ( csr_save_id ), + .csr_save_if_i ( csr_save_if ), + .csr_save_id_i ( csr_save_id ), .csr_restore_mret_i ( csr_restore_mret_id ), .csr_restore_dret_i ( csr_restore_dret_id ), - .csr_cause_i ( csr_cause ), - .csr_save_cause_i ( csr_save_cause ), + .csr_cause_i ( csr_cause ), + .csr_save_cause_i ( csr_save_cause ), // performance counter related signals - .if_valid_i ( if_valid ), - .id_valid_i ( id_valid ), - .is_compressed_i ( is_compressed_id ), - .is_decoding_i ( is_decoding ), + .if_valid_i ( if_valid ), + .id_valid_i ( id_valid ), + .is_compressed_i ( is_compressed_id ), + .is_decoding_i ( is_decoding ), - .imiss_i ( perf_imiss ), - .pc_set_i ( pc_set ), - .jump_i ( perf_jump ), - .branch_i ( perf_branch ), - .branch_taken_i ( perf_tbranch ), - .mem_load_i ( data_req_o & data_gnt_i & (~data_we_o) ), - .mem_store_i ( data_req_o & data_gnt_i & data_we_o ), + .imiss_i ( perf_imiss ), + .pc_set_i ( pc_set ), + .jump_i ( perf_jump ), + .branch_i ( perf_branch ), + .branch_taken_i ( perf_tbranch ), + .mem_load_i ( perf_load ), + .mem_store_i ( perf_store ), - .ext_counters_i ( ext_perf_counters_i ) + .ext_counters_i ( ext_perf_counters_i ) ); - - // CSR access - assign csr_access = csr_access_ex; - assign csr_wdata = alu_operand_a_ex; - assign csr_op = csr_op_ex; - - assign csr_addr = csr_num_e'(csr_access_ex ? alu_operand_b_ex[11:0] : 12'b0); - - `ifndef VERILATOR `ifdef TRACE_EXECUTION ibex_tracer ibex_tracer_i ( - .clk ( clk_i ), // always-running clock for tracing - .rst_n ( rst_ni ), + .clk_i ( clk_i ), // always-running clock for tracing + .rst_ni ( rst_ni ), - .fetch_enable ( fetch_enable_i ), - .core_id ( core_id_i ), - .cluster_id ( cluster_id_i ), + .fetch_enable_i ( fetch_enable_i ), + .core_id_i ( core_id_i ), + .cluster_id_i ( cluster_id_i ), - .pc ( id_stage_i.pc_id_i ), - .instr ( id_stage_i.instr ), - .compressed ( id_stage_i.is_compressed_i ), - .id_valid ( id_stage_i.id_valid_o ), - .is_decoding ( id_stage_i.is_decoding_o ), - .is_branch ( id_stage_i.branch_in_id ), - .branch_taken ( id_stage_i.branch_set_q ), - .pipe_flush ( id_stage_i.controller_i.pipe_flush_i ), - .mret_insn ( id_stage_i.controller_i.mret_insn_i ), - .dret_insn ( id_stage_i.controller_i.dret_insn_i ), - .ecall_insn ( id_stage_i.controller_i.ecall_insn_i ), - .ebrk_insn ( id_stage_i.controller_i.ebrk_insn_i ), - .csr_status ( id_stage_i.controller_i.csr_status_i ), - .rs1_value ( id_stage_i.operand_a_fw_id ), - .rs2_value ( id_stage_i.operand_b_fw_id ), + .pc_i ( id_stage_i.pc_id_i ), + .instr_i ( id_stage_i.instr ), + .compressed_i ( id_stage_i.is_compressed_i ), + .id_valid_i ( id_stage_i.id_valid_o ), + .is_decoding_i ( id_stage_i.is_decoding_o ), + .is_branch_i ( id_stage_i.branch_in_id ), + .branch_taken_i ( id_stage_i.branch_set_q ), + .pipe_flush_i ( id_stage_i.controller_i.pipe_flush_i ), + .mret_insn_i ( id_stage_i.controller_i.mret_insn_i ), + .dret_insn_i ( id_stage_i.controller_i.dret_insn_i ), + .ecall_insn_i ( id_stage_i.controller_i.ecall_insn_i ), + .ebrk_insn_i ( id_stage_i.controller_i.ebrk_insn_i ), + .csr_status_i ( id_stage_i.controller_i.csr_status_i ), + .rs1_value_i ( id_stage_i.operand_a_fw_id ), + .rs2_value_i ( id_stage_i.operand_b_fw_id ), - .lsu_value ( data_wdata_ex ), + .lsu_value_i ( data_wdata_ex ), - .ex_reg_addr ( id_stage_i.regfile_waddr_mux ), - .ex_reg_we ( id_stage_i.regfile_we_mux ), - .ex_reg_wdata ( id_stage_i.regfile_wdata_mux ), - .data_valid_lsu ( data_valid_lsu ), - .ex_data_addr ( data_addr_o ), - .ex_data_req ( data_req_o ), - .ex_data_gnt ( data_gnt_i ), - .ex_data_we ( data_we_o ), + .ex_reg_addr_i ( id_stage_i.regfile_waddr_mux ), + .ex_reg_we_i ( id_stage_i.regfile_we_mux ), + .ex_reg_wdata_i ( id_stage_i.regfile_wdata_mux ), + .data_valid_lsu_i ( data_valid_lsu ), + .ex_data_addr_i ( data_addr_o ), + .ex_data_req_i ( data_req_o ), + .ex_data_gnt_i ( data_gnt_i ), + .ex_data_we_i ( data_we_o ), - .ex_data_wdata ( data_wdata_o ), + .ex_data_wdata_i ( data_wdata_o ), - .lsu_reg_wdata ( regfile_wdata_lsu ), + .lsu_reg_wdata_i ( regfile_wdata_lsu ), - .imm_i_type ( id_stage_i.imm_i_type ), - .imm_s_type ( id_stage_i.imm_s_type ), - .imm_b_type ( id_stage_i.imm_b_type ), - .imm_u_type ( id_stage_i.imm_u_type ), - .imm_j_type ( id_stage_i.imm_j_type ), - .zimm_rs1_type ( id_stage_i.zimm_rs1_type ) + .imm_i_type_i ( id_stage_i.imm_i_type ), + .imm_s_type_i ( id_stage_i.imm_s_type ), + .imm_b_type_i ( id_stage_i.imm_b_type ), + .imm_u_type_i ( id_stage_i.imm_u_type ), + .imm_j_type_i ( id_stage_i.imm_j_type ), + .zimm_rs1_type_i ( id_stage_i.zimm_rs1_type ) ); `endif `endif diff --git a/rtl/ibex_cs_registers.sv b/rtl/ibex_cs_registers.sv index 518c2e2a..1554c938 100644 --- a/rtl/ibex_cs_registers.sv +++ b/rtl/ibex_cs_registers.sv @@ -31,8 +31,8 @@ module ibex_cs_registers #( parameter bit RV32M = 0 ) ( // Clock and Reset - input logic clk, - input logic rst_n, + input logic clk_i, + input logic rst_ni, // Core and Cluster ID input logic [3:0] core_id_i, @@ -69,7 +69,6 @@ module ibex_cs_registers #( input ibex_defines::exc_cause_e csr_cause_i, input logic csr_save_cause_i, - // Performance Counters input logic if_valid_i, // IF stage gives a new instruction input logic id_valid_i, // ID stage is done @@ -360,8 +359,8 @@ module ibex_cs_registers #( assign debug_ebreakm_o = dcsr_q.ebreakm; // actual registers - always_ff @(posedge clk, negedge rst_n) begin - if (!rst_n) begin + always_ff @(posedge clk_i, negedge rst_ni) begin + if (!rst_ni) begin mstatus_q <= '{ mie: 1'b0, mpie: 1'b0, @@ -533,8 +532,8 @@ module ibex_cs_registers #( end // Performance Counter Registers - always_ff @(posedge clk, negedge rst_n) begin - if (!rst_n) begin + always_ff @(posedge clk_i, negedge rst_ni) begin + if (!rst_ni) begin PCER_q <= '0; PCMR_q <= 2'h3; diff --git a/rtl/ibex_ex_block.sv b/rtl/ibex_ex_block.sv index 3b139c79..c0f7c4eb 100644 --- a/rtl/ibex_ex_block.sv +++ b/rtl/ibex_ex_block.sv @@ -29,8 +29,8 @@ module ibex_ex_block #( parameter bit RV32M = 1 ) ( - input logic clk, - input logic rst_n, + input logic clk_i, + input logic rst_ni, // ALU signals from ID stage input ibex_defines::alu_op_e alu_operator_i, @@ -114,8 +114,8 @@ module ibex_ex_block #( if (!MULT_TYPE) begin : gen_multdiv_slow ibex_multdiv_slow multdiv_i ( - .clk ( clk ), - .rst_n ( rst_n ), + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), .mult_en_i ( mult_en_i ), .div_en_i ( div_en_i ), .operator_i ( multdiv_operator_i ), @@ -132,8 +132,8 @@ module ibex_ex_block #( ); end else begin: gen_multdiv_fast ibex_multdiv_fast multdiv_i ( - .clk ( clk ), - .rst_n ( rst_n ), + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), .mult_en_i ( mult_en_i ), .div_en_i ( div_en_i ), .operator_i ( multdiv_operator_i ), diff --git a/rtl/ibex_fetch_fifo.sv b/rtl/ibex_fetch_fifo.sv index f7185ee0..72545deb 100644 --- a/rtl/ibex_fetch_fifo.sv +++ b/rtl/ibex_fetch_fifo.sv @@ -21,8 +21,8 @@ * this cycle already. */ module ibex_fetch_fifo ( - input logic clk, - input logic rst_n, + input logic clk_i, + input logic rst_ni, // control signals input logic clear_i, // clears the contents of the fifo @@ -182,8 +182,8 @@ module ibex_fetch_fifo ( // registers // /////////////// - always_ff @(posedge clk, negedge rst_n) begin - if (!rst_n) begin + always_ff @(posedge clk_i, negedge rst_ni) begin + if (!rst_ni) begin addr_Q <= '{default: '0}; rdata_Q <= '{default: '0}; valid_Q <= '0; @@ -205,6 +205,6 @@ module ibex_fetch_fifo ( //////////////// `ifndef VERILATOR assert property ( - @(posedge clk) (in_valid_i) |-> ((valid_Q[DEPTH-1] == 1'b0) || (clear_i == 1'b1)) ); + @(posedge clk_i) (in_valid_i) |-> ((valid_Q[DEPTH-1] == 1'b0) || (clear_i == 1'b1)) ); `endif endmodule diff --git a/rtl/ibex_id_stage.sv b/rtl/ibex_id_stage.sv index d85ac650..9cadef03 100644 --- a/rtl/ibex_id_stage.sv +++ b/rtl/ibex_id_stage.sv @@ -36,8 +36,8 @@ module ibex_id_stage #( parameter bit RV32M = 1, parameter bit RV32E = 0 ) ( - input logic clk, - input logic rst_n, + input logic clk_i, + input logic rst_ni, input logic test_en_i, @@ -328,8 +328,8 @@ module ibex_id_stage #( end ibex_register_file #( .RV32E(RV32E)) registers_i ( - .clk ( clk ), - .rst_n ( rst_n ), + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), .test_en_i ( test_en_i ), @@ -406,8 +406,8 @@ module ibex_id_stage #( //////////////// ibex_controller controller_i ( - .clk ( clk ), - .rst_n ( rst_n ), + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), .fetch_enable_i ( fetch_enable_i ), .ctrl_busy_o ( ctrl_busy_o ), @@ -492,8 +492,8 @@ module ibex_id_stage #( ////////////////////////// ibex_int_controller int_controller_i ( - .clk ( clk ), - .rst_n ( rst_n ), + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), // to controller .irq_req_ctrl_o ( irq_req_ctrl ), @@ -541,8 +541,8 @@ module ibex_id_stage #( //////////////////////////////// // ID-EX/WB Pipeline Register // //////////////////////////////// - always_ff @(posedge clk, negedge rst_n) begin : EX_WB_Pipeline_Register - if (!rst_n) begin + always_ff @(posedge clk_i, negedge rst_ni) begin : EX_WB_Pipeline_Register + if (!rst_ni) begin id_wb_fsm_cs <= IDLE; branch_set_q <= 1'b0; end else begin @@ -645,22 +645,22 @@ module ibex_id_stage #( `ifndef VERILATOR // make sure that branch decision is valid when jumping assert property ( - @(posedge clk) (branch_decision_i !== 1'bx || branch_in_id == 1'b0) ) else begin + @(posedge clk_i) (branch_decision_i !== 1'bx || branch_in_id == 1'b0) ) else begin $display("Branch decision is X"); $stop; end `ifdef CHECK_MISALIGNED assert property ( - @(posedge clk) (~data_misaligned_i) ) else $display("Misaligned memory access at %x",pc_id_i); + @(posedge clk_i) (~data_misaligned_i) ) else $display("Misaligned memory access at %x",pc_id_i); `endif // the instruction delivered to the ID stage should always be valid assert property ( - @(posedge clk) (instr_valid_i & (~illegal_c_insn_i)) |-> (!$isunknown(instr_rdata_i)) ) else + @(posedge clk_i) (instr_valid_i & (~illegal_c_insn_i)) |-> (!$isunknown(instr_rdata_i)) ) else $display("Instruction is valid, but has at least one X"); // make sure multicycles enable signals are unique assert property ( - @(posedge clk) ~(data_req_ex_o & multdiv_int_en )) else + @(posedge clk_i) ~(data_req_ex_o & multdiv_int_en )) else $display("Multicycles enable signals are not unique"); `endif diff --git a/rtl/ibex_if_stage.sv b/rtl/ibex_if_stage.sv index 208d8894..b43808ba 100644 --- a/rtl/ibex_if_stage.sv +++ b/rtl/ibex_if_stage.sv @@ -30,8 +30,8 @@ module ibex_if_stage #( parameter DM_HALT_ADDRESS = 32'h1A110800, parameter DM_EXCEPTION_ADDRESS = 32'h1A110808 ) ( - input logic clk, - input logic rst_n, + input logic clk_i, + input logic rst_ni, // the boot address is used to calculate the exception offsets input logic [31:0] boot_addr_i, // instruction request control @@ -129,8 +129,8 @@ module ibex_if_stage #( // prefetch buffer, caches a fixed number of instructions ibex_prefetch_buffer prefetch_buffer_i ( - .clk ( clk ), - .rst_n ( rst_n ), + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), .req_i ( req_i ), @@ -155,8 +155,8 @@ module ibex_if_stage #( // offset initialization state - always_ff @(posedge clk, negedge rst_n) begin - if (!rst_n) begin + always_ff @(posedge clk_i, negedge rst_ni) begin + if (!rst_ni) begin offset_in_init_q <= 1'b1; end else begin offset_in_init_q <= offset_in_init_d; @@ -219,8 +219,8 @@ module ibex_if_stage #( ); // IF-ID pipeline registers, frozen when the ID stage is stalled - always_ff @(posedge clk, negedge rst_n) begin : IF_ID_PIPE_REGISTERS - if (!rst_n) begin + always_ff @(posedge clk_i, negedge rst_ni) begin : IF_ID_PIPE_REGISTERS + if (!rst_ni) begin instr_valid_id_o <= 1'b0; instr_rdata_id_o <= '0; illegal_c_insn_id_o <= 1'b0; @@ -248,12 +248,12 @@ module ibex_if_stage #( `ifndef VERILATOR // the boot address needs to be aligned to 256 bytes assert property ( - @(posedge clk) (boot_addr_i[7:0] == 8'h00) ) + @(posedge clk_i) (boot_addr_i[7:0] == 8'h00) ) else $error("The provided boot address is not aligned to 256 bytes"); // there should never be a grant when there is no request assert property ( - @(posedge clk) (instr_gnt_i) |-> (instr_req_o) ) + @(posedge clk_i) (instr_gnt_i) |-> (instr_req_o) ) else $warning("There was a grant without a request"); `endif diff --git a/rtl/ibex_int_controller.sv b/rtl/ibex_int_controller.sv index f2a755dd..2087c674 100644 --- a/rtl/ibex_int_controller.sv +++ b/rtl/ibex_int_controller.sv @@ -20,8 +20,8 @@ * Interrupt Controller */ module ibex_int_controller ( - input logic clk, - input logic rst_n, + input logic clk_i, + input logic rst_ni, // irq_req for controller output logic irq_req_ctrl_o, @@ -50,8 +50,8 @@ module ibex_int_controller ( assign irq_req_ctrl_o = exc_ctrl_cs == IRQ_PENDING; assign irq_id_ctrl_o = irq_id_q; - always_ff @(posedge clk, negedge rst_n) begin - if (!rst_n) begin + always_ff @(posedge clk_i, negedge rst_ni) begin + if (!rst_ni) begin irq_id_q <= '0; exc_ctrl_cs <= IDLE; end else begin diff --git a/rtl/ibex_load_store_unit.sv b/rtl/ibex_load_store_unit.sv index 3fd3b269..e9ca5ea7 100644 --- a/rtl/ibex_load_store_unit.sv +++ b/rtl/ibex_load_store_unit.sv @@ -27,8 +27,8 @@ * and to align bytes and halfwords. */ module ibex_load_store_unit ( - input logic clk, - input logic rst_n, + input logic clk_i, + input logic rst_ni, // output to data memory output logic data_req_o, @@ -157,8 +157,8 @@ module ibex_load_store_unit ( // FF for rdata alignment and sign-extension - always_ff @(posedge clk, negedge rst_n) begin - if (!rst_n) begin + always_ff @(posedge clk_i, negedge rst_ni) begin + if (!rst_ni) begin data_type_q <= 2'h0; rdata_offset_q <= 2'h0; data_sign_ext_q <= 1'b0; @@ -277,8 +277,8 @@ module ibex_load_store_unit ( - always_ff @(posedge clk, negedge rst_n) begin - if (!rst_n) begin + always_ff @(posedge clk_i, negedge rst_ni) begin + if (!rst_ni) begin CS <= IDLE; rdata_q <= '0; data_misaligned_q <= '0; @@ -451,16 +451,15 @@ module ibex_load_store_unit ( // i.e. it should not be possible to get a grant without an rvalid for the // last request assert property ( - @(posedge clk) ((CS == WAIT_RVALID) && (data_gnt_i == 1'b1)) |-> (data_rvalid_i == 1'b1) ); + @(posedge clk_i) ((CS == WAIT_RVALID) && (data_gnt_i == 1'b1)) |-> (data_rvalid_i == 1'b1) ); // there should be no rvalid when we are in IDLE - assert property ( - @(posedge clk) (CS == IDLE) |-> (data_rvalid_i == 1'b0) ); + assert property ( @(posedge clk_i) (CS == IDLE) |-> (data_rvalid_i == 1'b0) ); // assert that errors are only sent at the same time as grant - assert property ( @(posedge clk) (data_err_i) |-> (data_gnt_i) ); + assert property ( @(posedge clk_i) (data_err_i) |-> (data_gnt_i) ); // assert that the address does not contain X when request is sent - assert property ( @(posedge clk) (data_req_o) |-> (!$isunknown(data_addr_o)) ); + assert property ( @(posedge clk_i) (data_req_o) |-> (!$isunknown(data_addr_o)) ); `endif endmodule diff --git a/rtl/ibex_multdiv_fast.sv b/rtl/ibex_multdiv_fast.sv index b37ca209..ba31521e 100644 --- a/rtl/ibex_multdiv_fast.sv +++ b/rtl/ibex_multdiv_fast.sv @@ -24,8 +24,8 @@ * 16x16 kernel multiplier and Long Division */ module ibex_multdiv_fast ( - input logic clk, - input logic rst_n, + input logic clk_i, + input logic rst_ni, input logic mult_en_i, input logic div_en_i, input ibex_defines::md_op_e operator_i, @@ -79,8 +79,8 @@ module ibex_multdiv_fast ( logic [32:0] res_adder_h; logic mult_is_ready; - always_ff @(posedge clk or negedge rst_n) begin : proc_mult_state_q - if (!rst_n) begin + always_ff @(posedge clk_i or negedge rst_ni) begin : proc_mult_state_q + if (!rst_ni) begin mult_state_q <= ALBL; mac_res_q <= '0; div_counter_q <= '0; diff --git a/rtl/ibex_multdiv_slow.sv b/rtl/ibex_multdiv_slow.sv index 54777dd1..ca2bf30e 100644 --- a/rtl/ibex_multdiv_slow.sv +++ b/rtl/ibex_multdiv_slow.sv @@ -21,8 +21,8 @@ * Baugh-Wooley multiplier and Long Division */ module ibex_multdiv_slow ( - input logic clk, - input logic rst_n, + input logic clk_i, + input logic rst_ni, input logic mult_en_i, input logic div_en_i, input ibex_defines::md_op_e operator_i, @@ -155,8 +155,8 @@ module ibex_multdiv_slow ( assign div_change_sign = sign_a ^ sign_b; assign rem_change_sign = sign_a; - always_ff @(posedge clk or negedge rst_n) begin : proc_multdiv_state_q - if (!rst_n) begin + always_ff @(posedge clk_i or negedge rst_ni) begin : proc_multdiv_state_q + if (!rst_ni) begin multdiv_state_q <= 5'h0; accum_window_q <= 33'h0; op_b_shift_q <= 33'h0; diff --git a/rtl/ibex_prefetch_buffer.sv b/rtl/ibex_prefetch_buffer.sv index 05d68a9d..2c2304e5 100644 --- a/rtl/ibex_prefetch_buffer.sv +++ b/rtl/ibex_prefetch_buffer.sv @@ -21,8 +21,8 @@ * paths to the instruction cache. */ module ibex_prefetch_buffer ( - input logic clk, - input logic rst_n, + input logic clk_i, + input logic rst_ni, input logic req_i, @@ -71,8 +71,8 @@ module ibex_prefetch_buffer ( ////////////////////////////////////////////// ibex_fetch_fifo fifo_i ( - .clk ( clk ), - .rst_n ( rst_n ), + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), .clear_i ( fifo_clear ), @@ -210,8 +210,8 @@ module ibex_prefetch_buffer ( // Registers // /////////////// - always_ff @(posedge clk, negedge rst_n) begin - if (!rst_n) begin + always_ff @(posedge clk_i, negedge rst_ni) begin + if (!rst_ni) begin CS <= IDLE; instr_addr_q <= '0; end else begin diff --git a/rtl/ibex_register_file.sv b/rtl/ibex_register_file.sv index f56e67bc..f68288a1 100644 --- a/rtl/ibex_register_file.sv +++ b/rtl/ibex_register_file.sv @@ -32,8 +32,8 @@ module ibex_register_file #( parameter DATA_WIDTH = 32 ) ( // Clock and Reset - input logic clk, - input logic rst_n, + input logic clk_i, + input logic rst_ni, input logic test_en_i, @@ -84,15 +84,15 @@ module ibex_register_file #( /////////////////////////////// prim_clock_gating CG_WE_GLOBAL ( - .clk_i ( clk ), + .clk_i ( clk_i ), .en_i ( we_a_i ), .test_en_i ( test_en_i ), .clk_o ( clk_int ) ); // use clk_int here, since otherwise we don't want to write anything anyway - always_ff @(posedge clk_int, negedge rst_n) begin : sample_waddr - if (!rst_n) begin + always_ff @(posedge clk_int, negedge rst_ni) begin : sample_waddr + if (!rst_ni) begin wdata_a_q <= '0; end else begin if (we_a_i) begin diff --git a/rtl/ibex_register_file_ff.sv b/rtl/ibex_register_file_ff.sv index 1927630d..a94755d6 100644 --- a/rtl/ibex_register_file_ff.sv +++ b/rtl/ibex_register_file_ff.sv @@ -30,8 +30,8 @@ module ibex_register_file #( parameter DATA_WIDTH = 32 ) ( // Clock and Reset - input logic clk, - input logic rst_n, + input logic clk_i, + input logic rst_ni, input logic test_en_i, @@ -65,8 +65,8 @@ module ibex_register_file #( end // loop from 1 to NUM_WORDS-1 as R0 is nil - always_ff @(posedge clk, negedge rst_n) begin - if (!rst_n) begin + always_ff @(posedge clk_i, negedge rst_ni) begin + if (!rst_ni) begin rf_reg_tmp <= '{default:'0}; end else begin for (int r = 1; r < NUM_WORDS; r++) begin diff --git a/rtl/ibex_tracer.sv b/rtl/ibex_tracer.sv index aba24fea..e2c1d00c 100644 --- a/rtl/ibex_tracer.sv +++ b/rtl/ibex_tracer.sv @@ -36,48 +36,48 @@ module ibex_tracer #( parameter REG_ADDR_WIDTH = 5 ) ( // Clock and Reset - input logic clk, - input logic rst_n, + input logic clk_i, + input logic rst_ni, - input logic fetch_enable, - input logic [3:0] core_id, - input logic [5:0] cluster_id, + input logic fetch_enable_i, + input logic [3:0] core_id_i, + input logic [5:0] cluster_id_i, - input logic [31:0] pc, - input logic [31:0] instr, - input logic compressed, - input logic id_valid, - input logic is_decoding, - input logic is_branch, - input logic branch_taken, - input logic pipe_flush, - input logic mret_insn, - input logic dret_insn, - input logic ecall_insn, - input logic ebrk_insn, - input logic csr_status, - input logic [31:0] rs1_value, - input logic [31:0] rs2_value, - input logic [31:0] lsu_value, + input logic [31:0] pc_i, + input logic [31:0] instr_i, + input logic compressed_i, + input logic id_valid_i, + input logic is_decoding_i, + input logic is_branch_i, + input logic branch_taken_i, + input logic pipe_flush_i, + input logic mret_insn_i, + input logic dret_insn_i, + input logic ecall_insn_i, + input logic ebrk_insn_i, + input logic csr_status_i, + input logic [31:0] rs1_value_i, + input logic [31:0] rs2_value_i, + input logic [31:0] lsu_value_i, - input logic [(REG_ADDR_WIDTH-1):0] ex_reg_addr, - input logic ex_reg_we, - input logic [31:0] ex_reg_wdata, - input logic data_valid_lsu, - input logic ex_data_req, - input logic ex_data_gnt, - input logic ex_data_we, - input logic [31:0] ex_data_addr, - input logic [31:0] ex_data_wdata, + input logic [(REG_ADDR_WIDTH-1):0] ex_reg_addr_i, + input logic ex_reg_we_i, + input logic [31:0] ex_reg_wdata_i, + input logic data_valid_lsu_i, + input logic ex_data_req_i, + input logic ex_data_gnt_i, + input logic ex_data_we_i, + input logic [31:0] ex_data_addr_i, + input logic [31:0] ex_data_wdata_i, - input logic [31:0] lsu_reg_wdata, + input logic [31:0] lsu_reg_wdata_i, - input logic [31:0] imm_i_type, - input logic [31:0] imm_s_type, - input logic [31:0] imm_b_type, - input logic [31:0] imm_u_type, - input logic [31:0] imm_j_type, - input logic [31:0] zimm_rs1_type + input logic [31:0] imm_i_type_i, + input logic [31:0] imm_s_type_i, + input logic [31:0] imm_b_type_i, + input logic [31:0] imm_u_type_i, + input logic [31:0] imm_j_type_i, + input logic [31:0] zimm_rs1_type_i ); integer f; @@ -130,8 +130,8 @@ module ibex_tracer #( begin $fwrite(f, "%t %15d %h %h %-36s", simtime, cycles, - pc, - instr, + pc_i, + instr_i, str); foreach(regs_write[i]) begin @@ -164,8 +164,8 @@ module ibex_tracer #( function void printRInstr(input string mnemonic); begin - regs_read.push_back('{rs1, rs1_value}); - regs_read.push_back('{rs2, rs2_value}); + regs_read.push_back('{rs1, rs1_value_i}); + regs_read.push_back('{rs2, rs2_value_i}); regs_write.push_back('{rd, 'x}); str = $sformatf("%-16s x%0d, x%0d, x%0d", mnemonic, rd, rs1, rs2); end @@ -173,54 +173,54 @@ module ibex_tracer #( function void printIInstr(input string mnemonic); begin - regs_read.push_back('{rs1, rs1_value}); + regs_read.push_back('{rs1, rs1_value_i}); regs_write.push_back('{rd, 'x}); - str = $sformatf("%-16s x%0d, x%0d, %0d", mnemonic, rd, rs1, $signed(imm_i_type)); + str = $sformatf("%-16s x%0d, x%0d, %0d", mnemonic, rd, rs1, $signed(imm_i_type_i)); end endfunction // printIInstr function void printIuInstr(input string mnemonic); begin - regs_read.push_back('{rs1, rs1_value}); + regs_read.push_back('{rs1, rs1_value_i}); regs_write.push_back('{rd, 'x}); - str = $sformatf("%-16s x%0d, x%0d, 0x%0x", mnemonic, rd, rs1, imm_i_type); + str = $sformatf("%-16s x%0d, x%0d, 0x%0x", mnemonic, rd, rs1, imm_i_type_i); end endfunction // printIuInstr function void printUInstr(input string mnemonic); begin regs_write.push_back('{rd, 'x}); - str = $sformatf("%-16s x%0d, 0x%0h", mnemonic, rd, {imm_u_type[31:12], 12'h000}); + str = $sformatf("%-16s x%0d, 0x%0h", mnemonic, rd, {imm_u_type_i[31:12], 12'h000}); end endfunction // printUInstr function void printUJInstr(input string mnemonic); begin regs_write.push_back('{rd, 'x}); - str = $sformatf("%-16s x%0d, %0d", mnemonic, rd, $signed(imm_j_type)); + str = $sformatf("%-16s x%0d, %0d", mnemonic, rd, $signed(imm_j_type_i)); end endfunction // printUJInstr function void printSBInstr(input string mnemonic); begin - regs_read.push_back('{rs1, rs1_value}); - regs_read.push_back('{rs2, rs2_value}); - str = $sformatf("%-16s x%0d, x%0d, %0d", mnemonic, rs1, rs2, $signed(imm_b_type)); + regs_read.push_back('{rs1, rs1_value_i}); + regs_read.push_back('{rs2, rs2_value_i}); + str = $sformatf("%-16s x%0d, x%0d, %0d", mnemonic, rs1, rs2, $signed(imm_b_type_i)); end endfunction // printSBInstr function void printCSRInstr(input string mnemonic); logic [11:0] csr; begin - csr = instr[31:20]; + csr = instr_i[31:20]; regs_write.push_back('{rd, 'x}); - if (!instr[14]) begin - regs_read.push_back('{rs1, rs1_value}); + if (!instr_i[14]) begin + regs_read.push_back('{rs1, rs1_value_i}); str = $sformatf("%-16s x%0d, x%0d, 0x%h", mnemonic, rd, rs1, csr); end else begin - str = $sformatf("%-16s x%0d, 0x%h, 0x%h", mnemonic, rd, zimm_rs1_type, csr); + str = $sformatf("%-16s x%0d, 0x%h, 0x%h", mnemonic, rd, zimm_rs1_type_i, csr); end end endfunction // printCSRInstr @@ -230,9 +230,9 @@ module ibex_tracer #( logic [2:0] size; begin // detect reg-reg load and find size - size = instr[14:12]; - if (instr[14:12] == 3'b111) begin - size = instr[30:28]; + size = instr_i[14:12]; + if (instr_i[14:12] == 3'b111) begin + size = instr_i[30:28]; end case (size) @@ -251,10 +251,10 @@ module ibex_tracer #( regs_write.push_back('{rd, 'x}); - if (instr[14:12] != 3'b111) begin + if (instr_i[14:12] != 3'b111) begin // regular load - regs_read.push_back('{rs1, rs1_value}); - str = $sformatf("%-16s x%0d, %0d(x%0d)", mnemonic, rd, $signed(imm_i_type), rs1); + regs_read.push_back('{rs1, rs1_value_i}); + str = $sformatf("%-16s x%0d, %0d(x%0d)", mnemonic, rd, $signed(imm_i_type_i), rs1); end else begin printMnemonic("INVALID"); end @@ -265,7 +265,7 @@ module ibex_tracer #( string mnemonic; begin - case (instr[13:12]) + case (instr_i[13:12]) 2'b00: mnemonic = "sb"; 2'b01: mnemonic = "sh"; 2'b10: mnemonic = "sw"; @@ -275,11 +275,11 @@ module ibex_tracer #( end endcase - if (!instr[14]) begin + if (!instr_i[14]) begin // regular store - regs_read.push_back('{rs2, rs2_value}); - regs_read.push_back('{rs1, rs1_value}); - str = $sformatf("%-16s x%0d, %0d(x%0d)", mnemonic, rs2, $signed(imm_s_type), rs1); + regs_read.push_back('{rs2, rs2_value_i}); + regs_read.push_back('{rs1, rs1_value_i}); + str = $sformatf("%-16s x%0d, %0d(x%0d)", mnemonic, rs2, $signed(imm_s_type_i), rs1); end else begin printMnemonic("INVALID"); end @@ -292,8 +292,8 @@ module ibex_tracer #( mailbox #(instr_trace_t) instr_wb = new (); // cycle counter - always_ff @(posedge clk, negedge rst_n) begin - if (!rst_n) begin + always_ff @(posedge clk_i, negedge rst_ni) begin + if (!rst_ni) begin cycles = 0; end else begin cycles = cycles + 1; @@ -302,9 +302,9 @@ module ibex_tracer #( // open/close output file for writing initial begin - wait(rst_n == 1'b1); - wait(fetch_enable == 1'b1); - $sformat(fn, "trace_core_%h_%h.log", cluster_id, core_id); + wait(rst_ni == 1'b1); + wait(fetch_enable_i == 1'b1); + $sformat(fn, "trace_core_%h_%h.log", cluster_id_i, core_id_i); $display("[TRACER] Output filename is: %s", fn); f = $fopen(fn, "w"); $fwrite(f, " Time Cycles PC Instr Mnemonic\n"); @@ -314,27 +314,27 @@ module ibex_tracer #( $fclose(f); end - assign rd = instr[`REG_D]; - assign rs1 = instr[`REG_S1]; - assign rs2 = instr[`REG_S2]; - assign rs3 = instr[`REG_S3]; + assign rd = instr_i[`REG_D]; + assign rs1 = instr_i[`REG_S1]; + assign rs2 = instr_i[`REG_S2]; + assign rs3 = instr_i[`REG_S3]; // log execution - always @(negedge clk) begin + always @(negedge clk_i) begin instr_trace_t trace; mem_acc_t mem_acc; // special case for WFI because we don't wait for unstalling there - if ( (id_valid || mret_insn || ecall_insn || pipe_flush || ebrk_insn || dret_insn || - csr_status || ex_data_req) && is_decoding) begin + if ( (id_valid_i || mret_insn_i || ecall_insn_i || pipe_flush_i || ebrk_insn_i || dret_insn_i || + csr_status_i || ex_data_req_i) && is_decoding_i) begin trace = new (); trace.simtime = $time; trace.cycles = cycles; - trace.pc = pc; - trace.instr = instr; + trace.pc = pc_i; + trace.instr = instr_i; // use casex instead of case inside due to ModelSim bug - casex (instr) + casex (instr_i) // Aliases 32'h00_00_00_13: trace.printMnemonic("nop"); // Regular opcodes @@ -395,45 +395,45 @@ module ibex_tracer #( {25'b?, {OPCODE_LOAD}}: trace.printLoadInstr(); {25'b?, {OPCODE_STORE}}: trace.printStoreInstr(); default: trace.printMnemonic("INVALID"); - endcase // unique case (instr) + endcase // unique case (instr_i) // replace register written back foreach(trace.regs_write[i]) begin - if ((trace.regs_write[i].addr == ex_reg_addr) && ex_reg_we) begin - trace.regs_write[i].value = ex_reg_wdata; + if ((trace.regs_write[i].addr == ex_reg_addr_i) && ex_reg_we_i) begin + trace.regs_write[i].value = ex_reg_wdata_i; end end // look for data accesses and log them - if (ex_data_req) begin + if (ex_data_req_i) begin - if (!ex_data_gnt) begin + if (!ex_data_gnt_i) begin //we wait until the the gnt comes - do @(negedge clk); - while (!ex_data_gnt); + do @(negedge clk_i); + while (!ex_data_gnt_i); end - mem_acc.addr = ex_data_addr; - mem_acc.we = ex_data_we; + mem_acc.addr = ex_data_addr_i; + mem_acc.we = ex_data_we_i; if (mem_acc.we) begin - mem_acc.wdata = ex_data_wdata; + mem_acc.wdata = ex_data_wdata_i; end else begin mem_acc.wdata = 'x; end //we wait until the the data instruction ends - do @(negedge clk); - while (!data_valid_lsu); + do @(negedge clk_i); + while (!data_valid_lsu_i); if (!mem_acc.we) begin //load operations foreach(trace.regs_write[i]) - trace.regs_write[i].value = lsu_reg_wdata; + trace.regs_write[i].value = lsu_reg_wdata_i; end trace.mem_access.push_back(mem_acc); end trace.printInstrTrace(); end - end // always @ (posedge clk) + end // always @ (posedge clk_i) endmodule