diff --git a/p/riscv_test.h b/p/riscv_test.h
index fe14f086..18fdc0a7 100644
--- a/p/riscv_test.h
+++ b/p/riscv_test.h
@@ -1,9 +1,11 @@
 // See LICENSE for license details.
+// clang-format off
 
 #ifndef _ENV_PHYSICAL_SINGLE_CORE_H
 #define _ENV_PHYSICAL_SINGLE_CORE_H
 
-#include "../encoding.h"
+#include "encoding.h"
+#include "ibex_macros.h"
 
 //-----------------------------------------------------------------------
 // Begin Macro
@@ -190,14 +192,13 @@ handle_exception:                                                       \
   1:    ori TESTNUM, TESTNUM, 1337;                                     \
   write_tohost:                                                         \
         sw TESTNUM, tohost, t5;                                         \
-        sw zero, tohost + 4, t5;                                        \
         j write_tohost;                                                 \
 reset_vector:                                                           \
         INIT_XREG;                                                      \
         RISCV_MULTICORE_DISABLE;                                        \
-        INIT_SATP;                                                      \
+      /*INIT_SATP; Ibex doesn't support supervisor mode */              \
         INIT_PMP;                                                       \
-        DELEGATE_NO_TRAPS;                                              \
+      /*DELEGATE_NO_TRAPS; Ibex doesn't support supervisor mode */      \
         li TESTNUM, 0;                                                  \
         la t0, trap_vector;                                             \
         csrw mtvec, t0;                                                 \
@@ -212,7 +213,7 @@ reset_vector:                                                           \
                (1 << CAUSE_MISALIGNED_FETCH) |                          \
                (1 << CAUSE_USER_ECALL) |                                \
                (1 << CAUSE_BREAKPOINT);                                 \
-        csrw medeleg, t0;                                               \
+      /*csrw medeleg, t0; Ibex doesn't support supervisor mode */       \
 1:      csrwi mstatus, 0;                                               \
         init;                                                           \
         EXTRA_INIT;                                                     \
@@ -236,20 +237,24 @@ reset_vector:                                                           \
 
 #define RVTEST_PASS                                                     \
         fence;                                                          \
-        li TESTNUM, 1;                                                  \
-        li a7, 93;                                                      \
-        li a0, 0;                                                       \
-        ecall
+        li x2, SIGNATURE_ADDR;                                          \
+        li x1, (FINISHED_IRQ << 8) | CORE_STATUS;                       \
+        sw x1, 0(x2);                                                   \
+        li x1, (TEST_PASS << 8) | TEST_RESULT;                          \
+        sw x1, 0(x2);                                                   \
+        2:;                                                             \
+        j 2b;
 
 #define TESTNUM gp
 #define RVTEST_FAIL                                                     \
         fence;                                                          \
-1:      beqz TESTNUM, 1b;                                               \
-        sll TESTNUM, TESTNUM, 1;                                        \
-        or TESTNUM, TESTNUM, 1;                                         \
-        li a7, 93;                                                      \
-        addi a0, TESTNUM, 0;                                            \
-        ecall
+        li x2, SIGNATURE_ADDR;                                          \
+        li x1, (FINISHED_IRQ << 8) | CORE_STATUS;                       \
+        sw x1, 0(x2);                                                   \
+        li x1, (TEST_FAIL << 8) | TEST_RESULT;                          \
+        sw x1, 0(x2);                                                   \
+        2:;                                                             \
+        j 2b;
 
 //-----------------------------------------------------------------------
 // Data Section Macro
@@ -260,8 +265,8 @@ reset_vector:                                                           \
 #define RVTEST_DATA_BEGIN                                               \
         EXTRA_DATA                                                      \
         .pushsection .tohost,"aw",@progbits;                            \
-        .align 6; .global tohost; tohost: .dword 0; .size tohost, 8;    \
-        .align 6; .global fromhost; fromhost: .dword 0; .size fromhost, 8;\
+        .align 6; .global tohost; tohost: .dword 0;                     \
+        .align 6; .global fromhost; fromhost: .dword 0;                 \
         .popsection;                                                    \
         .align 4; .global begin_signature; begin_signature: