From 8ba573d81941543b3a422d6d51e6c768b2c7de1d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jo=C3=A3o=20Vitor=20Rafael=20Chris=C3=B3stomo?= Date: Thu, 12 Mar 2020 21:45:17 -0300 Subject: [PATCH] Adding more geographical information --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index ffd00b2..28f77f3 100644 --- a/README.md +++ b/README.md @@ -1,5 +1,5 @@ # Maestro -This repository contains a 5 stage pipeline implementation of the RV32I ISA strongly inspired by [David Patterson's and John Hennessy's Computer Organization and Design RISC-V Edition.](https://www.amazon.com/dp/0128122757) The project is entirely academic, it was delevoped at Rio Grande do Norte's Federal University and it does not aim to be competitive against complex implementations. The rationale behind it was basically learning about RISC-V, the ISA, and processor design in general. If you want to deploy a RISC-V core, [I strongly recommend using a fully-featured and tested core instead.](https://github.com/riscv/riscv-wiki/wiki/RISC-V-Cores-and-SoCs) +This repository contains a 5 stage pipeline implementation of the RV32I ISA strongly inspired by [David Patterson's and John Hennessy's Computer Organization and Design RISC-V Edition.](https://www.amazon.com/dp/0128122757) The project is entirely academic, it was delevoped at Rio Grande do Norte's Federal University in Brazil and it does not aim to be competitive against complex implementations. The rationale behind it was basically learning about RISC-V, the ISA, and processor design in general. If you want to deploy a RISC-V core, [I strongly recommend using a fully-featured and tested core instead.](https://github.com/riscv/riscv-wiki/wiki/RISC-V-Cores-and-SoCs) ## Current Design - Entirely written in VHDL.