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==== Processor-Internal Data Cache (dCACHE)

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|=======================
| Hardware source files:  | neorv32_cache.vhd   | Generic cache module
| Software driver files:  | none                | _implicitly used_
| Top entity ports:       | none                |
| Configuration generics: | `DCACHE_EN`         | implement processor-internal data cache when `true`
|                         | `DCACHE_NUM_BLOCKS` | number of cache blocks (pages/lines)
|                         | `DCACHE_BLOCK_SIZE` | size of a cache block in bytes
| CPU interrupts:         | none |
| Access restrictions:  2+| none
|=======================


**Overview**

The processor features an optional data cache to improve performance when using memories with high
access latencies. The cache is connected directly to the CPU's data access interface and provides
full-transparent accesses. The cache is direct-mapped and uses "write-allocate" and "write-back" strategies.

.Cached/Uncached Accesses
[NOTE]
The data cache provides direct accesses (= uncached) to memory in order to access memory-mapped IO (like the
processor-internal IO/peripheral modules). All accesses that target the address range from `0xF0000000` to `0xFFFFFFFF`
will not be cached at all (see section <<_address_space>>). Direct/uncached accesses have **lower** priority than
cache block operations to allow continuous burst transfer and also to maintain logical instruction forward
progress / data coherency. Furthermore, atomic load-reservate and store-conditional instructions (<<_zalrsc_isa_extension>>)
will always **bypass** the cache.

.Caching Internal Memories
[NOTE]
The data cache is intended to accelerate data access to **processor-external** memories.
The CPU cache(s) should not be implemented when using only processor-internal data and instruction memories.

.Manual Cache Flush/Clear/Reload
[NOTE]
By executing the `fence(.i)` instruction the cache is flushed, cleared and a reload from main memory is triggered.

.Retrieve Cache Configuration from Software
[TIP]
Software can retrieve the cache configuration/layout from the <<_sysinfo_cache_configuration>> register.

.Bus Access Fault Handling
[NOTE]
The cache always loads a complete cache block (aligned to the block size) every time a
cache miss is detected. Each cached word from this block provides a single status bit that indicates if the
according bus access was successful or caused a bus error. Hence, the whole cache block remains valid even
if certain addresses inside caused a bus error. If the CPU accesses any of the faulty cache words, a
data bus error exception is raised.
