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==== General Purpose Input and Output Port (GPIO)

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|=======================
| Hardware source files:  | neorv32_gpio.vhd |
| Software driver files:  | neorv32_gpio.c |
|                         | neorv32_gpio.h |
| Top entity ports:       | `gpio_o` | 64-bit parallel output port
|                         | `gpio_i` | 64-bit parallel input port
| Configuration generics: | `IO_GPIO_NUM` | number of input/output pairs to implement (0..64)
| CPU interrupts:         | none |
| Access restrictions:  2+| privileged access only, non-32-bit write accesses are ignored
|=======================


**Overview**

The general purpose parallel IO unit provides a simple parallel input and output port. These ports can be used
chip-externally (for example to drive status LEDs, connect buttons, etc.) or chip-internally to provide control
signals for other IP modules.

The actual number of input/output pairs is defined by the `IO_GPIO_NUM` generic. When set to zero, the GPIO module
is excluded from synthesis and the output port `gpio_o` is tied to all-zero. If `IO_GPIO_NUM` is less than the
maximum value of 64, only the LSB-aligned bits in `gpio_o` and `gpio_i` are actually connected while the remaining
bits are tied to zero or are left unconnected, respectively.

.Access Atomicity
[NOTE]
The GPIO modules uses two memory-mapped registers (each 32-bit) each for accessing the input and
output signals. Since the CPU can only process 32-bit "at once" updating the entire output cannot
be performed within a single clock cycle.


**Register Map**

.GPIO unit register map (`struct NEORV32_GPIO`)
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|=======================
| Address      | Name [C]    | Bit(s) | R/W | Function
| `0xfffffc00` | `INPUT[0]`  | 31:0   | r/- | parallel input port pins 31:0
| `0xfffffc04` | `INPUT[1]`  | 31:0   | r/- | parallel input port pins 63:32
| `0xfffffc08` | `OUTPUT[0]` | 31:0   | r/w | parallel output port pins 31:0
| `0xfffffc0c` | `OUTPUT[1]` | 31:0   | r/w | parallel output port pins 63:32
|=======================
