diff --git a/CHANGELOG.md b/CHANGELOG.md index ac204495..69daac9e 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -29,6 +29,7 @@ mimpid = 0x01040312 -> Version 01.04.03.12 -> v1.4.3.12 | Date | Version | Comment | Ticket | |:----:|:-------:|:--------|:------:| +| 26.10.2024 | [**:rocket:1.10.6**](https://github.com/stnolting/neorv32/releases/tag/v1.10.6) | **New release** | | | 26.10.2024 | 1.10.5.11 | cleanup central makefile and linker script | [#1077](https://github.com/stnolting/neorv32/pull/1077) | | 21.10.2024 | 1.10.5.10 | :test_tube: rework linker script's ROM/IMEM default size (=16kB); add customization variable to all makefiles in `sw/example` | [#1072](https://github.com/stnolting/neorv32/pull/1072) | | 20.10.2024 | 1.10.5.9 | :warning: rework XIRQ controller; remove "interrupt pending" register `EIP` | [#1071](https://github.com/stnolting/neorv32/pull/1071) | diff --git a/docs/attrs.adoc b/docs/attrs.adoc index b096ceb1..501bb650 100644 --- a/docs/attrs.adoc +++ b/docs/attrs.adoc @@ -2,7 +2,7 @@ :email: stnolting@gmail.com :keywords: neorv32, risc-v, riscv, rv32, fpga, soft-core, vhdl, microcontroller, cpu, soc, processor, gcc, openocd, gdb, verilog, rtl, asip, asic, safety :description: A size-optimized, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL. -:revnumber: v1.10.5 +:revnumber: v1.10.6 :doctype: book :sectnums: :stem: diff --git a/rtl/core/neorv32_package.vhd b/rtl/core/neorv32_package.vhd index b5c4548c..9c318cc3 100644 --- a/rtl/core/neorv32_package.vhd +++ b/rtl/core/neorv32_package.vhd @@ -29,7 +29,7 @@ package neorv32_package is -- Architecture Constants ----------------------------------------------------------------- -- ------------------------------------------------------------------------------------------- - constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01100511"; -- hardware version + constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01100600"; -- hardware version constant archid_c : natural := 19; -- official RISC-V architecture ID constant XLEN : natural := 32; -- native data path width diff --git a/sw/svd/neorv32.svd b/sw/svd/neorv32.svd index 8655685c..bfe18b28 100644 --- a/sw/svd/neorv32.svd +++ b/sw/svd/neorv32.svd @@ -4,7 +4,7 @@ stnolting neorv32 RISC-V - 1.10.5 + 1.10.6 The NEORV32 RISC-V Processor