From 2611c89cbeb23ecff095321aa13577604533b775 Mon Sep 17 00:00:00 2001
From: Olof Kindgren <olof.kindgren@gmail.com>
Date: Mon, 13 Jun 2022 10:47:48 +0000
Subject: [PATCH] Update support for compliance tests version 2.7.4

---
 .github/workflows/ci.yml | 36 ++++++++++++++++++++++++------------
 1 file changed, 24 insertions(+), 12 deletions(-)

diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml
index d0570cc..6c71073 100644
--- a/.github/workflows/ci.yml
+++ b/.github/workflows/ci.yml
@@ -23,24 +23,36 @@ jobs:
     - name: setup workspace
       run: fusesoc library add serv $SERV
 
+    - name: Add MDU core as a library
+      run: fusesoc library add mdu https://github.com/zeeshanrafique23/mdu
+
     - name: build servant
-      run: fusesoc run --target=verilator_tb --build --build-root=servant_x servant
+      run: fusesoc run --target=verilator_tb --flag=mdu --build --build-root=servant_x servant --memsize=8388608 --compressed=1
 
-    - name: download risc-v compliance
-      run: git clone https://github.com/riscv/riscv-compliance --branch 1.0
+    - name: download riscv-arch-test version 2.7.4
+      run: git clone https://github.com/riscv-non-isa/riscv-arch-test.git --branch 2.7.4
 
-    - name: run RV32i compliance tests
+    - name: run RV32 I compliance tests
       run: |
-        cd $GITHUB_WORKSPACE/riscv-compliance
-        make TARGETDIR=$SERV/riscv-target RISCV_TARGET=serv RISCV_DEVICE=rv32i RISCV_ISA=rv32i TARGET_SIM=$GITHUB_WORKSPACE/servant_x/verilator_tb-verilator/Vservant_sim
+        cd $GITHUB_WORKSPACE/riscv-arch-test
+        make RISCV_PREFIX=riscv64-unknown-elf- TARGETDIR=$SERV/riscv-target RISCV_TARGET=serv RISCV_DEVICE=I TARGET_SIM=$GITHUB_WORKSPACE/servant_x/verilator_tb-verilator/Vservant_sim
 
-    - name: run RV32Zicsr compliance tests
+    - name: run RV32 C compliance tests
       run: |
-        cd $GITHUB_WORKSPACE/riscv-compliance
-        make TARGETDIR=$SERV/riscv-target RISCV_TARGET=serv RISCV_DEVICE=rv32i RISCV_ISA=rv32Zicsr TARGET_SIM=$GITHUB_WORKSPACE/servant_x/verilator_tb-verilator/Vservant_sim
+        cd $GITHUB_WORKSPACE/riscv-arch-test
+        make RISCV_PREFIX=riscv64-unknown-elf- TARGETDIR=$SERV/riscv-target RISCV_TARGET=serv RISCV_DEVICE=C TARGET_SIM=$GITHUB_WORKSPACE/servant_x/verilator_tb-verilator/Vservant_sim
 
-    - name: run RV32Zifencei compliance tests
+    - name: run RV32 M compliance tests
       run: |
-        cd $GITHUB_WORKSPACE/riscv-compliance
-        make TARGETDIR=$SERV/riscv-target RISCV_TARGET=serv RISCV_DEVICE=rv32i RISCV_ISA=rv32Zifencei TARGET_SIM=$GITHUB_WORKSPACE/servant_x/verilator_tb-verilator/Vservant_sim
+        cd $GITHUB_WORKSPACE/riscv-arch-test
+        make RISCV_PREFIX=riscv64-unknown-elf- TARGETDIR=$SERV/riscv-target RISCV_TARGET=serv RISCV_DEVICE=M TARGET_SIM=$GITHUB_WORKSPACE/servant_x/verilator_tb-verilator/Vservant_sim
 
+    - name: run RV32 Zifencei compliance tests
+      run: |
+        cd $GITHUB_WORKSPACE/riscv-arch-test
+        make RISCV_PREFIX=riscv64-unknown-elf- TARGETDIR=$SERV/riscv-target RISCV_TARGET=serv RISCV_DEVICE=Zifencei TARGET_SIM=$GITHUB_WORKSPACE/servant_x/verilator_tb-verilator/Vservant_sim
+
+#    - name: run RV32 privilege compliance tests
+#      run: |
+#        cd $GITHUB_WORKSPACE/riscv-arch-test
+#        make RISCV_PREFIX=riscv64-unknown-elf- TARGETDIR=$SERV/riscv-target RISCV_TARGET=serv RISCV_DEVICE=privilege TARGET_SIM=$GITHUB_WORKSPACE/servant_x/verilator_tb-verilator/Vservant_sim