diff --git a/rtl/serv_state.v b/rtl/serv_state.v
index f47ece7..cf2a181 100644
--- a/rtl/serv_state.v
+++ b/rtl/serv_state.v
@@ -128,7 +128,7 @@ endgenerate
     shift : Shift in during phase 1. Continue shifting between phases (except
             for the first cycle after init). Shift out during phase 2
     */
-   assign o_bufreg_en = (o_cnt_en & (o_init | o_ctrl_trap | i_branch_op)) | (i_shift_op & !stage_two_req & (i_sh_right | i_sh_done_r));
+   assign o_bufreg_en = (o_cnt_en & (o_init | o_ctrl_trap | i_branch_op)) | (i_shift_op & !stage_two_req & (i_sh_right | i_sh_done_r) & init_done);
 
    assign o_ibus_cyc = ibus_cyc & !i_rst;