diff --git a/servant/servant.v b/servant/servant.v
index 1bbcf26..ece4ce7 100644
--- a/servant/servant.v
+++ b/servant/servant.v
@@ -44,7 +44,7 @@ module servant
    wire 	wb_timer_cyc;
    wire [31:0] 	wb_timer_rdt;
 
-serv_arbiter serv_arbiter
+servant_arbiter servant_arbiter
    (
     .i_ibus_active (wb_cpu_ibus_cyc),
     .i_wb_cpu_dbus_adr (wb_cpu_dbus_adr),
@@ -74,7 +74,7 @@ serv_arbiter serv_arbiter
 `else
    parameter sim = 0;
 `endif
-   serv_mux #(sim) serv_mux
+   servant_mux #(sim) servant_mux
   (
    .i_clk (wb_clk),
    .i_rst (wb_rst),
@@ -130,7 +130,7 @@ serv_arbiter serv_arbiter
       .i_wb_dat (wb_mem_dat),
       .o_wb_rdt (wb_mem_rdt));
 
-   riscv_timer riscv_timer
+   servant_timer timer
      (.i_clk    (wb_clk),
       .i_rst    (wb_rst),
       .o_irq    (timer_irq),
@@ -139,7 +139,7 @@ serv_arbiter serv_arbiter
       .i_wb_dat (wb_timer_dat),
       .o_wb_dat (wb_timer_rdt));
 
-   wb_gpio gpio
+   servant_gpio gpio
      (.i_wb_clk (wb_clk),
       .i_wb_dat (wb_gpio_dat),
       .i_wb_cyc (wb_gpio_cyc),
diff --git a/servant/servant_arbiter.v b/servant/servant_arbiter.v
index 3d6f530..d8e902d 100644
--- a/servant/servant_arbiter.v
+++ b/servant/servant_arbiter.v
@@ -1,4 +1,4 @@
-module serv_arbiter
+module servant_arbiter
   (
    input wire 	      i_ibus_active,
    input wire [31:0]  i_wb_cpu_dbus_adr,
diff --git a/servant/servant_gpio.v b/servant/servant_gpio.v
index fb2646d..dd14ea5 100644
--- a/servant/servant_gpio.v
+++ b/servant/servant_gpio.v
@@ -1,4 +1,4 @@
-module wb_gpio
+module servant_gpio
   (
    input wire i_wb_clk,
    input wire i_wb_dat,
diff --git a/servant/servant_mux.v b/servant/servant_mux.v
index baf6912..072d764 100644
--- a/servant/servant_mux.v
+++ b/servant/servant_mux.v
@@ -4,7 +4,7 @@
  timer = 10
  testcon = 11
  */
-module serv_mux
+module servant_mux
   (
    input wire 	      i_clk,
    input wire 	      i_rst,
diff --git a/servant/servant_timer.v b/servant/servant_timer.v
index 2fbc80f..4b2f2e9 100644
--- a/servant/servant_timer.v
+++ b/servant/servant_timer.v
@@ -1,5 +1,5 @@
 `default_nettype none
-module riscv_timer
+module servant_timer
   (input wire 	     i_clk,
    input wire 	      i_rst,
    output reg 	      o_irq = 1'b0,