diff --git a/bench/serv_soc_tb.cpp b/bench/serv_soc_tb.cpp
index 1538d0c..f8cb929 100644
--- a/bench/serv_soc_tb.cpp
+++ b/bench/serv_soc_tb.cpp
@@ -55,7 +55,7 @@ int main(int argc, char **argv, char **env)
 
 	signal(SIGINT, INThandler);
 
-	top->wb_clk = 1;
+	top->i_clk = 1;
 	bool q = top->q;
 	while (!(done || Verilated::gotFinish())) {
 	  top->eval();
@@ -96,7 +96,7 @@ int main(int argc, char **argv, char **env)
 	      printf("%lu output q is %s\n", main_time, q ? "ON" : "OFF");
 	    }
 	    }*/
-	  top->wb_clk = !top->wb_clk;
+	  top->i_clk = !top->i_clk;
 	  main_time+=31.25;
 	}
 	if (tfp)
diff --git a/rtl/ice40_pll.v b/rtl/ice40_pll.v
new file mode 100644
index 0000000..8daad94
--- /dev/null
+++ b/rtl/ice40_pll.v
@@ -0,0 +1,40 @@
+`default_nettype none
+module ice40_pll
+  (
+   input  i_clk,
+   output o_clk,
+   output o_rst);
+
+   parameter PLL = "NONE";
+
+   wire   locked;
+
+   reg [1:0] rst_reg;
+   always @(posedge o_clk)
+     rst_reg <= {!locked, rst_reg[1]};
+   assign o_rst = rst_reg[0];
+
+   generate
+      if (PLL == "ICE40_CORE") begin
+	 SB_PLL40_CORE
+	   #(`include "pll.vh")
+	 pll
+	   (
+	    .LOCK(locked),
+	    .RESETB(1'b1),
+	    .BYPASS(1'b0),
+	    .REFERENCECLK(i_clk),
+	    .PLLOUTCORE(o_clk));
+      end else if (PLL == "ICE40_PAD") begin
+	 SB_PLL40_PAD
+	   #(`include "pll.vh")
+	 pll
+	   (
+	    .LOCK(locked),
+	    .RESETB(1'b1),
+	    .BYPASS(1'b0),
+	    .PACKAGEPIN (i_clk),
+	    .PLLOUTCORE(o_clk));
+      end
+   endgenerate
+endmodule
diff --git a/rtl/serv_clock_gen.v b/rtl/serv_clock_gen.v
index 5b47c33..558b05f 100644
--- a/rtl/serv_clock_gen.v
+++ b/rtl/serv_clock_gen.v
@@ -8,36 +8,11 @@ module serv_clock_gen
    parameter PLL = "NONE";
 
    generate
-      if (PLL == "ICE40_CORE") begin
-	 wire locked;
-	 SB_PLL40_CORE
-	   #(`include "pll.vh")
-	 pll
-	   (
-	    .LOCK(locked),
-	    .RESETB(1'b1),
-	    .BYPASS(1'b0),
-	    .REFERENCECLK(i_clk),
-	    .PLLOUTCORE(o_clk));
-	 reg [1:0] rst_reg;
-	 always @(posedge o_clk)
-	   rst_reg <= {!locked, rst_reg[1]};
-	 assign o_rst = rst_reg[0];
-      end else if (PLL == "ICE40_PAD") begin
-	 wire locked;
-	 SB_PLL40_PAD
-	   #(`include "pll.vh")
-	 pll
-	   (
-	    .LOCK(locked),
-	    .RESETB(1'b1),
-	    .BYPASS(1'b0),
-	    .PACKAGEPIN (i_clk),
-	    .PLLOUTCORE(o_clk));
-	 reg [1:0] rst_reg;
-	 always @(posedge o_clk)
-	   rst_reg <= {!locked, rst_reg[1]};
-	 assign o_rst = rst_reg[0];
+      if ((PLL == "ICE40_CORE") || (PLL == "ICE40_PAD")) begin
+	 ice40_pll #(.PLL (PLL)) pll
+	   (.i_clk (i_clk),
+	    .o_clk (o_clk),
+	    .o_rst (o_rst));
       end else begin
 	 assign o_clk = i_clk;
 
diff --git a/serv.core b/serv.core
index 0800a49..908b33d 100644
--- a/serv.core
+++ b/serv.core
@@ -20,6 +20,11 @@ filesets:
       - rtl/serv_top.v
     file_type : verilogSource
 
+  ice40_pll:
+    files:
+      - rtl/ice40_pll.v : {file_type : verilogSource}
+    depend : ["fusesoc:utils:generators"]
+
   mem_files:
     files:
       - sw/blinky.hex       : {copyto : blinky.hex}
@@ -41,7 +46,7 @@ filesets:
       - bench/serv_mux.v
       - bench/serv_wrapper.v
     file_type : verilogSource
-    depend : [wb_ram, "fusesoc:utils:generators"]
+    depend : [wb_ram]
 
   netlist:
     files: [synth.v : {file_type : verilogSource}]
@@ -65,7 +70,7 @@ targets:
 
   icebreaker:
     default_tool : icestorm
-    filesets : [core, mem_files, wrapper, icebreaker]
+    filesets : [core, ice40_pll, mem_files, wrapper, icebreaker]
     generate: [icebreaker_pll]
     parameters : [memfile, memsize, PLL=ICE40_PAD]
     tools:
@@ -81,7 +86,7 @@ targets:
 
   tinyfpga_bx:
     default_tool : icestorm
-    filesets : [core, mem_files, wrapper, tinyfpga_bx]
+    filesets : [core, ice40_pll, mem_files, wrapper, tinyfpga_bx]
     generate: [tinyfpga_bx_pll]
     parameters : [memfile, memsize, PLL=ICE40_CORE]
     tools: