diff --git a/data/alchitry_au.xdc b/data/alchitry_au.xdc
new file mode 100644
index 0000000..5853261
--- /dev/null
+++ b/data/alchitry_au.xdc
@@ -0,0 +1,16 @@
+## Clock signal
+set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports i_clk];
+create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports i_clk];
+
+## Reset
+set_property -dict {PACKAGE_PIN P6  IOSTANDARD LVCMOS33 } [get_ports i_rst_n];
+
+## LED
+## set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports q];
+
+## USB Serial output
+set_property -dict { PACKAGE_PIN P16 IOSTANDARD LVCMOS33 } [get_ports q]
+
+set_property CONFIG_VOLTAGE 3.3 [current_design]
+set_property CFGBVS VCCO [current_design]
+
diff --git a/servant.core b/servant.core
index a7f5efb..c438b03 100644
--- a/servant.core
+++ b/servant.core
@@ -55,6 +55,12 @@ filesets:
 
   alhambra   : {files: [data/alhambra.pcf : {file_type : PCF}]}
 
+  alchitry_au:
+    files:
+      - servant/servix_clock_gen.v : {file_type : verilogSource}
+      - servant/servix.v : {file_type : verilogSource}
+      - data/alchitry_au.xdc : {file_type : xdc}
+
   arty_a7_35t:
     files:
       - servant/servix_clock_gen.v : {file_type : verilogSource}
@@ -215,6 +221,15 @@ targets:
       vivado: {part : xc7a200t-fbg676-2}
     toplevel : servant_ac701
 
+  alchitry_au:
+    default_tool: vivado
+    description: Open-hardware Alchitry AU FPGA board
+    filesets : [mem_files, soc, alchitry_au]
+    parameters : [memfile, memsize, frequency=16, "mdu? (MDU=1)", WITH_RESET]
+    tools:
+      vivado: {part : xc7a35tftg256-1}
+    toplevel : servix
+
   alhambra:
     default_tool : icestorm
     description: Open-hardware iCE40HX4K FPGA board