diff --git a/rtl/Makefile b/rtl/Makefile
index f685efd6a..a99fd5628 100644
--- a/rtl/Makefile
+++ b/rtl/Makefile
@@ -21,13 +21,19 @@ LIB=
 
 CF=-CFLAGS '-std=c++11 -fms-extensions'
 
+CFRel=-CFLAGS '-std=c++11 -fms-extensions -O3 -DVL_THREADED'
+
 DEB=--trace --prof-cfuncs -DVL_DEBUG=1 
 
 
 MAKECPP=(cd obj_dir && make -j -f VVortex.mk OPT='-DVL_DEBUG' VL_DEBUG=1 DVL_DEBUG=1)
 
+MAKECPPRel=(cd obj_dir && make -j -f VVortex.mk)
+
 MAKEMULTICPP=(cd obj_dir && make -j -f VVortex_SOC.mk OPT='-DVL_DEBUG' VL_DEBUG=1 DVL_DEBUG=1)
 
+THREADS ?= $(shell python3 -c 'import multiprocessing as mp; print(max(1, mp.cpu_count() // 2))' )
+
 # -LDFLAGS '-lsystemc'
 VERILATOR:
 	echo "#define VCD_OFF" > simulate/tb_debug.h
@@ -37,6 +43,11 @@ VERILATORnoWarnings:
 	echo "#define VCD_OFF" > simulate/tb_debug.h
 	verilator $(COMP) -cc $(SINGLE_CORE) $(INCLUDE) $(EXE) $(LIB) $(CF)  $(WNO) $(DEB)
 
+VERILATORnoWarningsRel:
+	echo "#define VCD_OFF" > simulate/tb_debug.h
+	verilator $(COMP) -cc $(SINGLE_CORE) $(INCLUDE) $(EXE) $(LIB) $(CFRel)  $(WNO) --threads $(THREADS)
+
+
 VERILATORMULTInoWarnings:
 	echo "#define VCD_OFF" > simulate/tb_debug.h
 	verilator $(COMP) -cc $(MULTI_CORE) $(INCLUDE) $(MULTI_EXE) $(LIB) $(CF)  $(WNO) $(DEB)
@@ -58,6 +69,9 @@ debug: compdebug
 w: VERILATORnoWarnings
 	$(MAKECPP)
 
+wRel: VERILATORnoWarningsRel
+	$(MAKECPPRel)
+
 multicore: VERILATORMULTInoWarnings
 	$(MAKEMULTICPP)
 
@@ -67,5 +81,8 @@ dmulticore: compdebugmulti
 run: w
 	(cd obj_dir && ./VVortex)
 
+runRel: wRel
+	(cd obj_dir && ./VVortex)
+
 clean:
 	rm obj_dir/*
diff --git a/rtl/VX_writeback.v b/rtl/VX_writeback.v
index ee65dca8a..2cba499a9 100644
--- a/rtl/VX_writeback.v
+++ b/rtl/VX_writeback.v
@@ -75,7 +75,8 @@ module VX_writeback (
 		.out  ({use_wb_data                  , VX_writeback_inter.wb_valid, VX_writeback_inter.rd, VX_writeback_inter.wb, VX_writeback_inter.wb_warp_num, VX_writeback_inter.wb_pc})
 		);
 
-	reg[31:0] last_data_wb;
+
+	reg[31:0] last_data_wb /* verilator public */ ;
 	always @(posedge clk) begin
 		if ((|VX_writeback_inter.wb_valid) && (VX_writeback_inter.wb != 0) && (VX_writeback_inter.rd == 28)) begin
 			last_data_wb <= use_wb_data[0];
diff --git a/rtl/simulate/test_bench.cpp b/rtl/simulate/test_bench.cpp
index 8b2e7e9e2..0d03f4bf0 100644
--- a/rtl/simulate/test_bench.cpp
+++ b/rtl/simulate/test_bench.cpp
@@ -15,7 +15,8 @@ int main(int argc, char **argv)
 #define ALL_TESTS
 #ifdef ALL_TESTS
      bool passed = true;
-	 std::string tests[NUM_TESTS] = {
+
+  std::string tests[NUM_TESTS] = {
 	 	"../../emulator/riscv_tests/rv32ui-p-add.hex",
 	 	"../../emulator/riscv_tests/rv32ui-p-addi.hex",
 	 	"../../emulator/riscv_tests/rv32ui-p-and.hex",
diff --git a/rtl/simulate/test_bench.h b/rtl/simulate/test_bench.h
index 69e2d257d..e8c5f2229 100644
--- a/rtl/simulate/test_bench.h
+++ b/rtl/simulate/test_bench.h
@@ -13,6 +13,7 @@
 #include "VX_define.h"
 #include "ram.h"
 #include "VVortex.h"
+#include "VVortex__Syms.h"
 #include "verilated.h"
 
 #include "tb_debug.h"
@@ -462,7 +463,7 @@ bool Vortex::simulate(std::string file_to_simulate)
 
     std::cerr << "New Total Cycles: " << (this->stats_total_cycles) << "\n";
 
-    int status = (unsigned int) vortex->Vortex__DOT__vx_back_end__DOT__VX_wb__DOT__last_data_wb & 0xf;
+    int status = (unsigned int) vortex->Vortex->vx_back_end->VX_wb->last_data_wb & 0xf;
 
     // std::cout << "Last wb: " << std::hex << ((unsigned int) vortex->Vortex__DOT__vx_back_end__DOT__VX_wb__DOT__last_data_wb) << "\n";