From 43d8922f649f58633e03d9c14cdba889e3870bc5 Mon Sep 17 00:00:00 2001
From: Blaise Tine <tinebp@yahoo.com>
Date: Tue, 21 Apr 2020 15:21:59 -0400
Subject: [PATCH] minor update

---
 hw/rtl/VX_csr_data.v              | 6 +++---
 hw/rtl/VX_scheduler.v             | 5 ++---
 hw/rtl/VX_warp_sched.v            | 2 +-
 hw/rtl/cache/VX_cache_req_queue.v | 2 +-
 4 files changed, 7 insertions(+), 8 deletions(-)

diff --git a/hw/rtl/VX_csr_data.v b/hw/rtl/VX_csr_data.v
index 4caf47c44..63adfc397 100644
--- a/hw/rtl/VX_csr_data.v
+++ b/hw/rtl/VX_csr_data.v
@@ -78,7 +78,7 @@ module VX_csr_data (
 
     assign read_csr_data =  read_cycle    ? cycle[31:0] :
                                 read_cycleh   ? cycle[63:32] :
-                                read_instret  ? instret[31:0] :
-                                read_instreth ? instret[63:32] :
-                                                {{20{1'b0}}, csr[read_addr]};
+                                    read_instret  ? instret[31:0] :
+                                        read_instreth ? instret[63:32] :
+                                            {{20{1'b0}}, csr[read_addr]};
 endmodule : VX_csr_data
diff --git a/hw/rtl/VX_scheduler.v b/hw/rtl/VX_scheduler.v
index a8d598e63..bcb12c72b 100644
--- a/hw/rtl/VX_scheduler.v
+++ b/hw/rtl/VX_scheduler.v
@@ -47,10 +47,9 @@ module VX_scheduler (
                          || (gpr_stage_delay && (is_mem || is_exec))
                          || (exec_delay && is_exec);
 
-    integer i;
-    integer w;
-    always @(posedge clk) begin
+    integer i, w;
 
+    always @(posedge clk) begin
         if (reset) begin
             for (w = 0; w < `NUM_WARPS; w=w+1) begin
                 for (i = 0; i < 32; i = i + 1) begin
diff --git a/hw/rtl/VX_warp_sched.v b/hw/rtl/VX_warp_sched.v
index b6d4f455d..1004131d6 100644
--- a/hw/rtl/VX_warp_sched.v
+++ b/hw/rtl/VX_warp_sched.v
@@ -88,7 +88,7 @@ module VX_warp_sched (
     wire wstall_this_cycle;
 
     reg[`NUM_THREADS-1:0] thread_masks[`NUM_WARPS-1:0];
-    reg[31:0]     warp_pcs[`NUM_WARPS-1:0];
+    reg[31:0] warp_pcs[`NUM_WARPS-1:0];
 
     // barriers
     reg[`NUM_WARPS-1:0] barrier_stall_mask[(`NUM_BARRIERS-1):0];
diff --git a/hw/rtl/cache/VX_cache_req_queue.v b/hw/rtl/cache/VX_cache_req_queue.v
index 2c6a3f77e..b1fb07c17 100644
--- a/hw/rtl/cache/VX_cache_req_queue.v
+++ b/hw/rtl/cache/VX_cache_req_queue.v
@@ -173,7 +173,7 @@ module VX_cache_req_queue #(
 
     always @(posedge clk) begin
         if (reset) begin
-             use_per_valids   <= 0;
+            use_per_valids    <= 0;
             use_per_addr      <= 0;
             use_per_writedata <= 0;
             use_per_rd        <= 0;