diff --git a/hw/rtl/libs/VX_fifo_queue.sv b/hw/rtl/libs/VX_fifo_queue.sv
index f3cc65b7b..c7a4aab6d 100644
--- a/hw/rtl/libs/VX_fifo_queue.sv
+++ b/hw/rtl/libs/VX_fifo_queue.sv
@@ -110,9 +110,12 @@ module VX_fifo_queue #(
         if (OUT_REG != 0) begin : g_out_reg
             reg [DATAW-1:0] data_out_r;
             wire going_empty = (ALM_EMPTY == 1) ? alm_empty : (size[ADDRW-1:0] == ADDRW'(1));
+            wire bypass = push && (empty || (going_empty && pop));
             always @(posedge clk) begin
-                if (pop || (push && empty)) begin
-                    data_out_r <= (empty || going_empty) ? data_in : data_out_w;
+                if (bypass) begin
+                    data_out_r <= data_in;
+                end else if (pop) begin
+                    data_out_r <= data_out_w;
                 end
             end
             assign data_out = data_out_r;