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mt76: mt7615: initialize radar specs from host driver
Introduce dfs radar pattern specs in mt7615 driver in order to make dfs debugging easier. Radar pulse/pattern thresholds are taken from vendor SDK. Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org> Signed-off-by: Felix Fietkau <nbd@nbd.name>
This commit is contained in:
Lorenzo Bianconi
Felix Fietkau
parent
d9d8be11f8
commit
2ce73efe0f
5 changed files with 166 additions and 0 deletions
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@ -17,6 +17,44 @@
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#define to_rssi(field, rxv) ((FIELD_GET(field, rxv) - 220) / 2)
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static const struct mt7615_dfs_radar_spec etsi_radar_specs = {
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.pulse_th = { 40, -10, -80, 800, 3360, 128, 5200 },
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.radar_pattern = {
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[5] = { 1, 0, 6, 32, 28, 0, 17, 990, 5010, 1, 1 },
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[6] = { 1, 0, 9, 32, 28, 0, 27, 615, 5010, 1, 1 },
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[7] = { 1, 0, 15, 32, 28, 0, 27, 240, 445, 1, 1 },
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[8] = { 1, 0, 12, 32, 28, 0, 42, 240, 510, 1, 1 },
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[9] = { 1, 1, 0, 0, 0, 0, 14, 2490, 3343, 0, 0, 12, 32, 28 },
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[10] = { 1, 1, 0, 0, 0, 0, 14, 2490, 3343, 0, 0, 15, 32, 24 },
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[11] = { 1, 1, 0, 0, 0, 0, 14, 823, 2510, 0, 0, 18, 32, 28 },
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[12] = { 1, 1, 0, 0, 0, 0, 14, 823, 2510, 0, 0, 27, 32, 24 },
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},
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};
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static const struct mt7615_dfs_radar_spec fcc_radar_specs = {
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.pulse_th = { 40, -10, -80, 800, 3360, 128, 5200 },
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.radar_pattern = {
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[0] = { 1, 0, 9, 32, 28, 0, 13, 508, 3076, 1, 1 },
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[1] = { 1, 0, 12, 32, 28, 0, 17, 140, 240, 1, 1 },
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[2] = { 1, 0, 8, 32, 28, 0, 22, 190, 510, 1, 1 },
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[3] = { 1, 0, 6, 32, 28, 0, 32, 190, 510, 1, 1 },
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[4] = { 1, 0, 9, 255, 28, 0, 13, 323, 343, 1, 32 },
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},
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};
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static const struct mt7615_dfs_radar_spec jp_radar_specs = {
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.pulse_th = { 40, -10, -80, 800, 3360, 128, 5200 },
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.radar_pattern = {
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[0] = { 1, 0, 8, 32, 28, 0, 13, 508, 3076, 1, 1 },
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[1] = { 1, 0, 12, 32, 28, 0, 17, 140, 240, 1, 1 },
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[2] = { 1, 0, 8, 32, 28, 0, 22, 190, 510, 1, 1 },
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[3] = { 1, 0, 6, 32, 28, 0, 32, 190, 510, 1, 1 },
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[4] = { 1, 0, 9, 32, 28, 0, 13, 323, 343, 1, 32 },
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[13] = { 1, 0, 8, 32, 28, 0, 14, 3836, 3856, 1, 1 },
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[14] = { 1, 0, 8, 32, 28, 0, 14, 3990, 4010, 1, 1 },
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},
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};
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static struct mt76_wcid *mt7615_rx_get_wcid(struct mt7615_dev *dev,
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u8 idx, bool unicast)
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{
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@ -1685,6 +1723,40 @@ static int mt7615_dfs_start_radar_detector(struct mt7615_phy *phy)
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return 0;
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}
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static int
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mt7615_dfs_init_radar_specs(struct mt7615_phy *phy)
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{
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const struct mt7615_dfs_radar_spec *radar_specs;
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struct mt7615_dev *dev = phy->dev;
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int err, i;
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switch (dev->mt76.region) {
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case NL80211_DFS_FCC:
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radar_specs = &fcc_radar_specs;
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err = mt7615_mcu_set_fcc5_lpn(dev, 8);
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if (err < 0)
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return err;
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break;
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case NL80211_DFS_ETSI:
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radar_specs = &etsi_radar_specs;
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break;
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case NL80211_DFS_JP:
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radar_specs = &jp_radar_specs;
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break;
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default:
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return -EINVAL;
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}
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for (i = 0; i < ARRAY_SIZE(radar_specs->radar_pattern); i++) {
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err = mt7615_mcu_set_radar_th(dev, i,
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&radar_specs->radar_pattern[i]);
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if (err < 0)
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return err;
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}
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return mt7615_mcu_set_pulse_th(dev, &radar_specs->pulse_th);
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}
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int mt7615_dfs_init_radar_detector(struct mt7615_phy *phy)
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{
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struct cfg80211_chan_def *chandef = &phy->mt76->chandef;
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@ -1706,6 +1778,12 @@ int mt7615_dfs_init_radar_detector(struct mt7615_phy *phy)
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if (phy->dfs_state == chandef->chan->dfs_state)
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return 0;
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err = mt7615_dfs_init_radar_specs(phy);
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if (err < 0) {
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phy->dfs_state = -1;
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goto stop;
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}
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phy->dfs_state = chandef->chan->dfs_state;
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if (chandef->chan->flags & IEEE80211_CHAN_RADAR) {
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@ -306,6 +306,38 @@ struct mt7615_tx_free {
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#define MT_TXS6_F1_RCPI_1 GENMASK(15, 8)
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#define MT_TXS6_F1_RCPI_0 GENMASK(7, 0)
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struct mt7615_dfs_pulse {
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u32 max_width; /* us */
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int max_pwr; /* dbm */
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int min_pwr; /* dbm */
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u32 min_stgr_pri; /* us */
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u32 max_stgr_pri; /* us */
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u32 min_cr_pri; /* us */
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u32 max_cr_pri; /* us */
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};
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struct mt7615_dfs_pattern {
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u8 enb;
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u8 stgr;
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u8 min_crpn;
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u8 max_crpn;
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u8 min_crpr;
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u8 min_pw;
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u8 max_pw;
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u32 min_pri;
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u32 max_pri;
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u8 min_crbn;
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u8 max_crbn;
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u8 min_stgpn;
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u8 max_stgpn;
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u8 min_stgpr;
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};
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struct mt7615_dfs_radar_spec {
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struct mt7615_dfs_pulse pulse_th;
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struct mt7615_dfs_pattern radar_pattern[16];
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};
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enum mt7615_cipher_type {
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MT_CIPHER_NONE,
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MT_CIPHER_WEP40,
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@ -1333,6 +1333,54 @@ int mt7615_mcu_rdd_cmd(struct mt7615_dev *dev,
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&req, sizeof(req), true);
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}
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int mt7615_mcu_set_fcc5_lpn(struct mt7615_dev *dev, int val)
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{
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struct {
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u16 tag;
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u16 min_lpn;
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} req = {
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.tag = 0x1,
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.min_lpn = val,
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};
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return __mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD_SET_RDD_TH,
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&req, sizeof(req), true);
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}
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int mt7615_mcu_set_pulse_th(struct mt7615_dev *dev,
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const struct mt7615_dfs_pulse *pulse)
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{
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struct {
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u16 tag;
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struct mt7615_dfs_pulse pulse;
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} req = {
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.tag = 0x3,
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};
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memcpy(&req.pulse, pulse, sizeof(*pulse));
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return __mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD_SET_RDD_TH,
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&req, sizeof(req), true);
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}
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int mt7615_mcu_set_radar_th(struct mt7615_dev *dev, int index,
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const struct mt7615_dfs_pattern *pattern)
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{
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struct {
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u16 tag;
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u16 radar_type;
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struct mt7615_dfs_pattern pattern;
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} req = {
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.tag = 0x2,
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.radar_type = index,
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};
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memcpy(&req.pattern, pattern, sizeof(*pattern));
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return __mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD_SET_RDD_TH,
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&req, sizeof(req), true);
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}
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int mt7615_mcu_rdd_send_pattern(struct mt7615_dev *dev)
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{
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struct {
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@ -152,6 +152,7 @@ enum {
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MCU_EXT_CMD_MAC_INIT_CTRL = 0x46,
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MCU_EXT_CMD_BCN_OFFLOAD = 0x49,
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MCU_EXT_CMD_SET_RX_PATH = 0x4e,
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MCU_EXT_CMD_SET_RDD_TH = 0x7c,
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MCU_EXT_CMD_SET_RDD_PATTERN = 0x7d,
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};
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@ -46,6 +46,8 @@
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struct mt7615_vif;
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struct mt7615_sta;
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struct mt7615_dfs_pulse;
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struct mt7615_dfs_pattern;
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enum mt7615_hw_txq_id {
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MT7615_TXQ_MAIN,
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@ -341,6 +343,11 @@ void mt7615_mac_work(struct work_struct *work);
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void mt7615_txp_skb_unmap(struct mt76_dev *dev,
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struct mt76_txwi_cache *txwi);
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int mt76_dfs_start_rdd(struct mt7615_dev *dev, bool force);
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int mt7615_mcu_set_fcc5_lpn(struct mt7615_dev *dev, int val);
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int mt7615_mcu_set_pulse_th(struct mt7615_dev *dev,
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const struct mt7615_dfs_pulse *pulse);
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int mt7615_mcu_set_radar_th(struct mt7615_dev *dev, int index,
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const struct mt7615_dfs_pattern *pattern);
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int mt7615_dfs_init_radar_detector(struct mt7615_phy *phy);
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int mt7615_init_debugfs(struct mt7615_dev *dev);
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