Your window into the Elastic Stack
Updated 2026-09-22 16:18:02 -06:00
Milk-V Jupiter RISC-V Kernel Full History
Updated 2026-09-22 15:00:46 -06:00
CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.
Updated 2026-09-22 12:41:06 -06:00
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
Updated 2026-09-22 12:30:51 -06:00
A browser based Pokémon fangame heavily inspired by the roguelite genre.
Updated 2026-09-22 06:44:58 -06:00
Base images for Immich containers
Updated 2026-09-22 06:26:07 -06:00
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
Updated 2026-09-22 05:56:14 -06:00
Updated 2026-09-21 17:17:24 -06:00
Self-hosted audiobook and podcast server
Updated 2026-09-21 16:02:46 -06:00
🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
asip
axi
cpu
embedded
fpga
microcontroller
neorv32
on-chip-debbuger
processor
risc-v
riscv
rtl
rtos
rv32
safety
soc
soft-core
system-on-chip
verilog
vhdl
Updated 2026-09-20 10:03:03 -06:00
C++ Interface for communicating with Cricut x-y plotters. Originally developed by vangdfang on github.
Updated 2026-09-19 22:21:52 -06:00
Invidious companion for handling video streams - based on youtube.js
Updated 2026-09-19 10:38:40 -06:00
Notes from attending CppCon 2026
Updated 2026-09-19 10:10:44 -06:00
Invidious is an alternative front-end to YouTube
Updated 2026-09-18 14:44:25 -06:00
Milk-V Jupiter GPU information. Contents unclear, storing for completeness.
Updated 2026-09-18 04:56:22 -06:00