Your window into the Elastic Stack
Updated 2026-06-23 12:31:51 -06:00
A browser based Pokémon fangame heavily inspired by the roguelite genre.
Updated 2026-06-23 11:22:36 -06:00
Updated 2026-06-23 04:26:23 -06:00
Helm chart implementation of Immich
Updated 2026-06-22 18:51:04 -06:00
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
Updated 2026-06-22 17:38:48 -06:00
Invidious is an alternative front-end to YouTube
Updated 2026-06-22 14:43:38 -06:00
Invidious companion for handling video streams - based on youtube.js
Updated 2026-06-22 14:33:25 -06:00
CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.
Updated 2026-06-22 07:33:55 -06:00
Milk-V Jupiter RISC-V Kernel Full History
Updated 2026-06-22 01:48:59 -06:00
Self-hosted audiobook and podcast server
Updated 2026-06-20 16:06:32 -06:00
The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH Zurich and Ibex work from lowRISC.
Updated 2026-06-19 09:57:54 -06:00
Your self hosted YouTube media server
Updated 2026-06-19 04:55:22 -06:00
Base images for Immich containers
Updated 2026-06-18 17:04:38 -06:00
Docker image for Prowlarr/Prowlarr
Updated 2026-06-17 02:45:26 -06:00
🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
asip
axi
cpu
embedded
fpga
microcontroller
neorv32
on-chip-debbuger
processor
risc-v
riscv
rtl
rtos
rv32
safety
soc
soft-core
system-on-chip
verilog
vhdl
Updated 2026-06-16 12:51:25 -06:00