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iommu/arm-smmu-qcom: Add an adreno-smmu-priv callback to get pagefault info

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Add a callback in adreno-smmu-priv to read interesting SMMU
registers to provide an opportunity for a richer debug experience
in the GPU driver.

Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210610214431.539029-3-robdclark@gmail.com
Signed-off-by: Rob Clark <robdclark@chromium.org>
This commit is contained in:
Jordan Crouse 2021-06-10 14:44:10 -07:00 • committed by Rob Clark
parent f8f934c180
commit ab5df7b953
3 changed files with 49 additions and 1 deletions
Download patch file Download diff file Expand all files Collapse all files

17
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
View file

@ -32,6 +32,22 @@ static void qcom_adreno_smmu_write_sctlr(struct arm_smmu_device *smmu, int idx,
arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_SCTLR, reg); arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_SCTLR, reg);
} }
static void qcom_adreno_smmu_get_fault_info(const void *cookie,
struct adreno_smmu_fault_info *info)
{
struct arm_smmu_domain *smmu_domain = (void *)cookie;
struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
struct arm_smmu_device *smmu = smmu_domain->smmu;
info->fsr = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_FSR);
info->fsynr0 = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_FSYNR0);
info->fsynr1 = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_FSYNR1);
info->far = arm_smmu_cb_readq(smmu, cfg->cbndx, ARM_SMMU_CB_FAR);
info->cbfrsynra = arm_smmu_gr1_read(smmu, ARM_SMMU_GR1_CBFRSYNRA(cfg->cbndx));
info->ttbr0 = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_TTBR0);
info->contextidr = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_CONTEXTIDR);
}
#define QCOM_ADRENO_SMMU_GPU_SID 0 #define QCOM_ADRENO_SMMU_GPU_SID 0
static bool qcom_adreno_smmu_is_gpu_device(struct device *dev) static bool qcom_adreno_smmu_is_gpu_device(struct device *dev)
@ -156,6 +172,7 @@ static int qcom_adreno_smmu_init_context(struct arm_smmu_domain *smmu_domain,
priv->cookie = smmu_domain; priv->cookie = smmu_domain;
priv->get_ttbr1_cfg = qcom_adreno_smmu_get_ttbr1_cfg; priv->get_ttbr1_cfg = qcom_adreno_smmu_get_ttbr1_cfg;
priv->set_ttbr0_cfg = qcom_adreno_smmu_set_ttbr0_cfg; priv->set_ttbr0_cfg = qcom_adreno_smmu_set_ttbr0_cfg;
priv->get_fault_info = qcom_adreno_smmu_get_fault_info;
return 0; return 0;
} }

2
drivers/iommu/arm/arm-smmu/arm-smmu.h
View file

@ -224,6 +224,8 @@ enum arm_smmu_cbar_type {
#define ARM_SMMU_CB_FSYNR0 0x68 #define ARM_SMMU_CB_FSYNR0 0x68
#define ARM_SMMU_FSYNR0_WNR BIT(4) #define ARM_SMMU_FSYNR0_WNR BIT(4)
#define ARM_SMMU_CB_FSYNR1 0x6c
#define ARM_SMMU_CB_S1_TLBIVA 0x600 #define ARM_SMMU_CB_S1_TLBIVA 0x600
#define ARM_SMMU_CB_S1_TLBIASID 0x610 #define ARM_SMMU_CB_S1_TLBIASID 0x610
#define ARM_SMMU_CB_S1_TLBIVAL 0x620 #define ARM_SMMU_CB_S1_TLBIVAL 0x620

31
include/linux/adreno-smmu-priv.h
View file

@ -8,6 +8,32 @@
#include <linux/io-pgtable.h> #include <linux/io-pgtable.h>
/**
* struct adreno_smmu_fault_info - container for key fault information
*
* @far: The faulting IOVA from ARM_SMMU_CB_FAR
* @ttbr0: The current TTBR0 pagetable from ARM_SMMU_CB_TTBR0
* @contextidr: The value of ARM_SMMU_CB_CONTEXTIDR
* @fsr: The fault status from ARM_SMMU_CB_FSR
* @fsynr0: The value of FSYNR0 from ARM_SMMU_CB_FSYNR0
* @fsynr1: The value of FSYNR1 from ARM_SMMU_CB_FSYNR0
* @cbfrsynra: The value of CBFRSYNRA from ARM_SMMU_GR1_CBFRSYNRA(idx)
*
* This struct passes back key page fault information to the GPU driver
* through the get_fault_info function pointer.
* The GPU driver can use this information to print informative
* log messages and provide deeper GPU specific insight into the fault.
*/
struct adreno_smmu_fault_info {
u64 far;
u64 ttbr0;
u32 contextidr;
u32 fsr;
u32 fsynr0;
u32 fsynr1;
u32 cbfrsynra;
};
/** /**
* struct adreno_smmu_priv - private interface between adreno-smmu and GPU * struct adreno_smmu_priv - private interface between adreno-smmu and GPU
* *
@ -17,6 +43,8 @@
* @set_ttbr0_cfg: Set the TTBR0 config for the GPUs context bank. A * @set_ttbr0_cfg: Set the TTBR0 config for the GPUs context bank. A
* NULL config disables TTBR0 translation, otherwise * NULL config disables TTBR0 translation, otherwise
* TTBR0 translation is enabled with the specified cfg * TTBR0 translation is enabled with the specified cfg
* @get_fault_info: Called by the GPU fault handler to get information about
* the fault
* *
* The GPU driver (drm/msm) and adreno-smmu work together for controlling * The GPU driver (drm/msm) and adreno-smmu work together for controlling
* the GPU's SMMU instance. This is by necessity, as the GPU is directly * the GPU's SMMU instance. This is by necessity, as the GPU is directly
@ -31,6 +59,7 @@ struct adreno_smmu_priv {
const void *cookie; const void *cookie;
const struct io_pgtable_cfg *(*get_ttbr1_cfg)(const void *cookie); const struct io_pgtable_cfg *(*get_ttbr1_cfg)(const void *cookie);
int (*set_ttbr0_cfg)(const void *cookie, const struct io_pgtable_cfg *cfg); int (*set_ttbr0_cfg)(const void *cookie, const struct io_pgtable_cfg *cfg);
void (*get_fault_info)(const void *cookie, struct adreno_smmu_fault_info *info);
}; };
#endif /* __ADRENO_SMMU_PRIV_H */ #endif /* __ADRENO_SMMU_PRIV_H */