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fpga: dfl: afu: add header sub feature support

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The port header register set is always present for port, it is mainly
for capability, control and status of the ports that AFU connected to.

This patch implements header sub feature support. Below user interfaces
are created by this patch.

Sysfs interface:
* /sys/class/fpga_region/<regionX>/<dfl-port.x>/id
  Read-only. Port ID.

Ioctl interface:
* DFL_FPGA_PORT_RESET
  Reset the FPGA Port and its AFU.

Signed-off-by: Tim Whisonant <tim.whisonant@intel.com>
Signed-off-by: Enno Luebbers <enno.luebbers@intel.com>
Signed-off-by: Shiva Rao <shiva.rao@intel.com>
Signed-off-by: Christopher Rauer <christopher.rauer@intel.com>
Signed-off-by: Xiao Guangrong <guangrong.xiao@linux.intel.com>
Signed-off-by: Wu Hao <hao.wu@intel.com>
Acked-by: Alan Tull <atull@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Wu Hao 2018-06-30 08:53:32 +08:00 • committed by Greg Kroah-Hartman
parent 47c1b19c16
commit e4664c0ee4
3 changed files with 102 additions and 1 deletions
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17
include/uapi/linux/fpga-dfl.h
View file

@ -29,8 +29,11 @@
#define DFL_FPGA_MAGIC 0xB6
#define DFL_FPGA_BASE 0
#define DFL_PORT_BASE 0x40
#define DFL_FME_BASE 0x80
/* Common IOCTLs for both FME and AFU file descriptor */
/**
* DFL_FPGA_GET_API_VERSION - _IO(DFL_FPGA_MAGIC, DFL_FPGA_BASE + 0)
*
@ -49,6 +52,20 @@
#define DFL_FPGA_CHECK_EXTENSION _IO(DFL_FPGA_MAGIC, DFL_FPGA_BASE + 1)
/* IOCTLs for AFU file descriptor */
/**
* DFL_FPGA_PORT_RESET - _IO(DFL_FPGA_MAGIC, DFL_PORT_BASE + 0)
*
* Reset the FPGA Port and its AFU. No parameters are supported.
* Userspace can do Port reset at any time, e.g. during DMA or PR. But
* it should never cause any system level issue, only functional failure
* (e.g. DMA or PR operation failure) and be recoverable from the failure.
* Return: 0 on success, -errno of failure
*/
#define DFL_FPGA_PORT_RESET _IO(DFL_FPGA_MAGIC, DFL_PORT_BASE + 0)
/* IOCTLs for FME file descriptor */
/**